// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  mqm_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2020/3/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/03/24 21:55:25 Create file
// ******************************************************************************

#ifndef MQM_REG_OFFSET_H
#define MQM_REG_OFFSET_H

/* MQM_TOP Base address of Module's Register */
#define CSR_MQM_TOP_BASE (0x2000)

/* **************************************************************************** */
/*                      MQM_TOP Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_TOP_MQM_EDITION_REG (CSR_MQM_TOP_BASE + 0x0)            /* Version Register */
#define CSR_MQM_TOP_MQM_INITCTAB_START_REG (CSR_MQM_TOP_BASE + 0x4)     /* 配置表初始化使能寄存器 */
#define CSR_MQM_TOP_MQM_INITCTAB_DONE_REG (CSR_MQM_TOP_BASE + 0x8)      /* 配置表初始化状态寄存器 */
#define CSR_MQM_TOP_MQM_CFG_OK_REG (CSR_MQM_TOP_BASE + 0xC)             /* MQM 配置完成寄存器 */
#define CSR_MQM_TOP_MQM_INITLOGIC_DONE_REG (CSR_MQM_TOP_BASE + 0x10)    /* 芯片逻辑初始化状态寄存器 */
#define CSR_MQM_TOP_MQM_TOP_INT_VECTOR_REG (CSR_MQM_TOP_BASE + 0x30)    /* MQM Interrupt Vector  Register */
#define CSR_MQM_TOP_MQM_TOP_INT_REG (CSR_MQM_TOP_BASE + 0x34)           /* MQM Interrupt Register */
#define CSR_MQM_TOP_MQM_TOP_INT_EN_REG (CSR_MQM_TOP_BASE + 0x38)        /* MQM Interrupt Mask Register */
#define CSR_MQM_TOP_VF_FLUSH_DONE_INT_REG (CSR_MQM_TOP_BASE + 0x3C)     /* VF FLUSH finish done Interrupt register. */
#define CSR_MQM_TOP_MQM_RX_CNP_E0_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x40) /* Receive Ring CNP E0 error int */
#define CSR_MQM_TOP_MQM_RX_CNP_E1_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x44) /* Receive Ring CNP E1 error int */
#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_REG (CSR_MQM_TOP_BASE + 0x48) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_MASK_REG \
    (CSR_MQM_TOP_BASE + 0x4C) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_TOP_USE_HOST_BITMAP_REG (CSR_MQM_TOP_BASE + 0x80)             /* HOST使用指示寄存器 */
#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB0_REG (CSR_MQM_TOP_BASE + 0x84)         /* DB TYPE映射表0 */
#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB1_REG (CSR_MQM_TOP_BASE + 0x88)         /* DB TYPE映射表1 */
#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB2_REG (CSR_MQM_TOP_BASE + 0x8C)         /* DB TYPE映射表2 */
#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB3_REG (CSR_MQM_TOP_BASE + 0x90)         /* DB TYPE映射表3 */
#define CSR_MQM_TOP_MQM_CMQ_ENQ_MODE_CFG_REG (CSR_MQM_TOP_BASE + 0x94)        /* MQM CMQ ENQ MODE CFG */
#define CSR_MQM_TOP_MQM_MAX_DMA_CRDT_CFG_REG (CSR_MQM_TOP_BASE + 0x98)        /* Config value for dma credit */
#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_0_REG (CSR_MQM_TOP_BASE + 0x9C)        /* MQM SOC QUEUE USE PF 31 To 0 CFG */
#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_1_REG (CSR_MQM_TOP_BASE + 0xA0)        /* MQM SOC QUEUE USE PF 31 To 0 CFG */
#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_2_REG (CSR_MQM_TOP_BASE + 0xA4)        /* MQM SOC QUEUE USE PF 31 To 0 CFG */
#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_3_REG (CSR_MQM_TOP_BASE + 0xA8)        /* MQM SOC QUEUE USE PF 31 To 0 CFG */
#define CSR_MQM_TOP_MQM_PF_CFG_REG (CSR_MQM_TOP_BASE + 0xAC)                  /* MQM PF CFG */
#define CSR_MQM_TOP_MQM_VF_FLUSH_CFG_REG (CSR_MQM_TOP_BASE + 0x100)           /* VF FLUSH配置寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x104)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x108)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x10C)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x110)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x114)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x118)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x11C)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x120)  /* VF FLUSH NMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x124) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x128) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x12C) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x130) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x134) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x138) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x13C) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x140) /* VF FLUSH NFMQ 对应配置ID寄存器 */
#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_NUM_REG \
    (CSR_MQM_TOP_BASE + 0x144) /* The number of Remote RDMA Read VF flush txqid */
#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_BADDR_REG \
    (CSR_MQM_TOP_BASE + 0x148) /* The base address of Remote RDMA Read VF flush */
#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x14C)   /* The number of Send Queue  VF flush txqid */
#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x150) /* The base address of Send Queue VF flush */
#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_NUM_REG \
    (CSR_MQM_TOP_BASE + 0x154) /* The number of Filterable stateful RQ queue VF flush */
#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_BADDR_REG \
    (CSR_MQM_TOP_BASE + 0x158) /* The base address of Filterable stateful RQ queue VF flush */
#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x15C)   /* The number of uCode CMQ VF flush */
#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x160) /* The base address of uCode CMQ VF flush */
#define CSR_MQM_TOP_VF_FLUSH_LNIC_SQ_TXQ_INFO_REG \
    (CSR_MQM_TOP_BASE + 0x164) /* The information of L2NIC SQ Queue VF flush */
#define CSR_MQM_TOP_VF_FLUSH_LNIC_RQ_TXQ_INFO_REG \
    (CSR_MQM_TOP_BASE + 0x168)                                        /* The information of L2NIC RQ Queue VF flush */
#define CSR_MQM_TOP_MQM_VF_FLUSH_DONE_REG (CSR_MQM_TOP_BASE + 0x174)  /* Record the status for flush when VF Flush */
#define CSR_MQM_TOP_MQM_UNCRT_ERR_MASK_REG (CSR_MQM_TOP_BASE + 0x200) /* MQM Urgency Interrupt Mask Register。 */
#define CSR_MQM_TOP_MQM_UNCRT_ERR_CLR_REG (CSR_MQM_TOP_BASE + 0x204)  /* MQM Urgency Interrupt Clear Register。 */
#define CSR_MQM_TOP_MQM_VF_COUNT_CFG_REG \
    (CSR_MQM_TOP_BASE +                  \
        0x304) /* cfg vfid that mqm need statistics the number of doorbell which is belong to designated vfid */
#define CSR_MQM_TOP_MQM_RX_DESIGNATE_VFID_CNT_REG                                                                     \
    (CSR_MQM_TOP_BASE + 0x308) /* Statics the number of doorbell which mqm received and belongs to the designate vfid \
                                */
#define CSR_MQM_TOP_MQM_FILT_DESIGNATE_VFID_CNT_REG \
    (CSR_MQM_TOP_BASE +                             \
        0x30C) /* Statics the number of doorbell which filted by mqm and belongs to the designate vfid */
#define CSR_MQM_TOP_MQM_TX_SM_DESIGNATE_VFID_CNT_REG \
    (CSR_MQM_TOP_BASE + 0x310) /* Statics the number of doorbell which send to sm and belongs to the designate vfid */
#define CSR_MQM_TOP_MQM_TX_QU_DESIGNATE_VFID_CNT_REG \
    (CSR_MQM_TOP_BASE + 0x314) /* Statics the number of doorbell which send to qu and belongs to the designate vfid */
#define CSR_MQM_TOP_MQM_RCV_TILE_API_OP_ERR_CNT_REG \
    (CSR_MQM_TOP_BASE + 0x318) /* Statics the number of API from tile with opid err */
#define CSR_MQM_TOP_MQM_RCV_TILE_FAST_CNP_API_CNT_REG \
    (CSR_MQM_TOP_BASE + 0x31C) /* Statics the number of FAST CNP API from Tile */
#define CSR_MQM_TOP_MQM_RCV_TILE_CNP_API_E0E1_CNT_REG \
    (CSR_MQM_TOP_BASE + 0x320) /* Statics the number of FAST CNP E0E1 API from Tile */
#define CSR_MQM_TOP_MQM_ND_RS_RQST_CREDIT_REG \
    (CSR_MQM_TOP_BASE + 0x324)                                     /* MQM node interface with Ring credit request cnt */
#define CSR_MQM_TOP_MQM_TOP_FIFO_ST_REG (CSR_MQM_TOP_BASE + 0x328) /* MQM TOP fifo full and empt state */

/* MQM_ENQC Base address of Module's Register */
#define CSR_MQM_ENQC_BASE (0x4000)

/* **************************************************************************** */
/*                      MQM_ENQC Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_ENQC_ENQC_RW_RSV0_REG (CSR_MQM_ENQC_BASE + 0x0)          /* enqc rw reserved register 0 */
#define CSR_MQM_ENQC_ENQC_RW_RSV1_REG (CSR_MQM_ENQC_BASE + 0x4)          /* enqc rw reserved register 1 */
#define CSR_MQM_ENQC_ENQC_RW_RSV2_REG (CSR_MQM_ENQC_BASE + 0x8)          /* enqc rw reserved register 2 */
#define CSR_MQM_ENQC_ENQC_RW_RSV3_REG (CSR_MQM_ENQC_BASE + 0xC)          /* enqc rw reserved register 3 */
#define CSR_MQM_ENQC_ENQC_INDRECT_CTRL_REG (CSR_MQM_ENQC_BASE + 0x10)    /* ENQC Indirect access ctrl Register */
#define CSR_MQM_ENQC_ENQC_INDRECT_TIMEOUT_REG (CSR_MQM_ENQC_BASE + 0x14) /* ENQC Indirect Access Timeout Register */
#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_0_REG (CSR_MQM_ENQC_BASE + 0x18)  /* ENQC Indirect Access Data Register0 */
#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_1_REG (CSR_MQM_ENQC_BASE + 0x1C)  /* ENQC Indirect Access Data Register1 */
#define CSR_MQM_ENQC_ENQC_INT_VECTOR_REG (CSR_MQM_ENQC_BASE + 0x20)      /* enqc int vector */
#define CSR_MQM_ENQC_ENQC_INT_REG (CSR_MQM_ENQC_BASE + 0x24)             /* enqc int */
#define CSR_MQM_ENQC_ENQC_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x28)          /* enqc int mask */
#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR0_REG (CSR_MQM_ENQC_BASE + 0x2C)    /* RAM ECC ONE BIT ERR */
#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR1_REG (CSR_MQM_ENQC_BASE + 0x30)    /* RAM ECC TWO BIT ERR */
#define CSR_MQM_ENQC_TABLE_RD_INVLD_INT_REG (CSR_MQM_ENQC_BASE + 0x34)   /* table read invalid */
#define CSR_MQM_ENQC_VFPF_TO_HOST_ID_INT_REG (CSR_MQM_ENQC_BASE + 0x38)  /* VF or PF map to HOST ID err */
#define CSR_MQM_ENQC_QU_ENQC_DB_IF_INT_REG (CSR_MQM_ENQC_BASE + 0x3C)    /* QU to ENQC db interface err */
#define CSR_MQM_ENQC_CPI_DISCARD_INT_REG (CSR_MQM_ENQC_BASE + 0x40)      /* this int indicate cpi discard doorbell */
#define CSR_MQM_ENQC_ENQC_FIFO_INT_REG (CSR_MQM_ENQC_BASE + 0x44) /* enqc fifo write overflow and read underflow */
#define CSR_MQM_ENQC_ENQC_FIFO_INT_EN_REG \
    (CSR_MQM_ENQC_BASE + 0x48)                                  /* enqc fifo write overflow mask and read overflow */
#define CSR_MQM_ENQC_ENQC_QF_INT_REG (CSR_MQM_ENQC_BASE + 0x4C) /* enqc queue filter error int */
#define CSR_MQM_ENQC_RX_RING_E0_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x50) /* Receive Ring E0 error int */
#define CSR_MQM_ENQC_RX_RING_E1_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x54) /* Receive Ring E1 error int */
#define CSR_MQM_ENQC_ENQC_TXQID_OVFL_VF_RANGE_INT_REG \
    (CSR_MQM_ENQC_BASE + 0x58) /* The int that filter doorbell's txqid overflow the range of VF */
#define CSR_MQM_ENQC_ENQC_NONF_NUM_OVFL_THR_INT_REG \
    (CSR_MQM_ENQC_BASE + 0x5C) /* The int that The number of non-filter doorbell overflow the threshold */
#define CSR_MQM_ENQC_ENQC_ERR_TYP_DB_INT_REG (CSR_MQM_ENQC_BASE + 0x60) /* The int that error type doorbell for mqm */
#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ0_REG (CSR_MQM_ENQC_BASE + 0x80)   /* ENQC memory ecc insert request Register0 */
#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ1_REG (CSR_MQM_ENQC_BASE + 0x84)   /* ENQC memory ecc insert request Register1 */
#define CSR_MQM_ENQC_ENQC_QU_DB_IF_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x88) /* qu to enqc uncorrect int enable */
#define CSR_MQM_ENQC_ENQC_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x8C)          /* enqc uncorrect int enable */
#define CSR_MQM_ENQC_ENQC_SENDQ_BASE_ADDR_REG \
    (CSR_MQM_ENQC_BASE + 0xB0)                                       /* SQ TXQID filter base address in filter space */
#define CSR_MQM_ENQC_ENQC_SENDQ_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xB4) /* SQ TXQID filter limite in filter space */
#define CSR_MQM_ENQC_ENQC_TASKIO_BASE_ADDR_REG \
    (CSR_MQM_ENQC_BASE + 0xB8) /* TASKIO TXQID filter base address in filter space */
#define CSR_MQM_ENQC_ENQC_TASKIO_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xBC) /* TASKIO TXQID filter limite in filter space */
#define CSR_MQM_ENQC_ENQC_RDMA_BASE_ADDR_REG \
    (CSR_MQM_ENQC_BASE + 0xC0)                                      /* RDMA TXQID filter base address in filter space */
#define CSR_MQM_ENQC_ENQC_RDMA_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xC4) /* RDMA TXQID filter limite in filter space */
#define CSR_MQM_ENQC_ENQC_FTXQID_BASE_ADDR_REG \
    (CSR_MQM_ENQC_BASE + 0xC8)                                        /* RQ TXQID filter base address in filter space */
#define CSR_MQM_ENQC_ENQC_FTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xCC) /* RQ TXQID filter limite in filter space */
#define CSR_MQM_ENQC_ENQC_UTXQID_BASE_ADDR_REG \
    (CSR_MQM_ENQC_BASE + 0xD0) /* uCode TXQID filter base address in filter space */
#define CSR_MQM_ENQC_ENQC_UTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xD4) /* uCode TXQID filter limite in filter space */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_0_REG \
    (CSR_MQM_ENQC_BASE + 0xD8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_1_REG \
    (CSR_MQM_ENQC_BASE + 0xDC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_2_REG \
    (CSR_MQM_ENQC_BASE + 0xE0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_3_REG \
    (CSR_MQM_ENQC_BASE + 0xE4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_4_REG \
    (CSR_MQM_ENQC_BASE + 0xE8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_5_REG \
    (CSR_MQM_ENQC_BASE + 0xEC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_6_REG \
    (CSR_MQM_ENQC_BASE + 0xF0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_7_REG \
    (CSR_MQM_ENQC_BASE + 0xF4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_0_REG \
    (CSR_MQM_ENQC_BASE + 0xF8) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_1_REG \
    (CSR_MQM_ENQC_BASE + 0xFC) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_2_REG \
    (CSR_MQM_ENQC_BASE + 0x100) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_3_REG \
    (CSR_MQM_ENQC_BASE + 0x104) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_4_REG \
    (CSR_MQM_ENQC_BASE + 0x108) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_5_REG \
    (CSR_MQM_ENQC_BASE + 0x10C) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_6_REG \
    (CSR_MQM_ENQC_BASE + 0x110) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_7_REG \
    (CSR_MQM_ENQC_BASE + 0x114) /* soc pf based TXQID range for l2nic sq and l2nic rq */
#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x118) /* Host L2NIC SQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_LIMIT_REG \
    (CSR_MQM_ENQC_BASE + 0x11C) /* Host L2NIC SQ PI store limite in pi store space */
#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x120) /* Host L2NIC RQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_LIMIT_REG \
    (CSR_MQM_ENQC_BASE + 0x124) /* Host L2NIC RQ PI store limite in pi store space */
#define CSR_MQM_ENQC_ENQC_SQ_CNT_BADDR_REG (CSR_MQM_ENQC_BASE + 0x128) /* SQ PI store base address in pi store space \
                                                                        */
#define CSR_MQM_ENQC_ENQC_SQ_CNT_LIMIT_REG (CSR_MQM_ENQC_BASE + 0x12C) /* SQ PI store limite in pi store space */
#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_LIMIT_REG \
    (CSR_MQM_ENQC_BASE + 0x130) /* Host L2NIC CMQ PI store limite in pi store space */
#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x134)   /* enqc pf range map to port */
#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x138)   /* enqc pf range map to port */
#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x13C)   /* enqc pf range map to port */
#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x140)   /* enqc pf range map to port */
#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_4_REG (CSR_MQM_ENQC_BASE + 0x144)   /* enqc pf range map to port */
#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x148)   /* enqc vf range map to port */
#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x14C)   /* enqc vf range map to port */
#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x150)   /* enqc vf range map to port */
#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x154)   /* enqc vf range map to port */
#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x158)  /* enqc lvf range map to port */
#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x15C)  /* enqc lvf range map to port */
#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x160)  /* enqc lvf range map to port */
#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x164)  /* enqc lvf range map to port */
#define CSR_MQM_ENQC_ENQC_ENQC_CFG_REG (CSR_MQM_ENQC_BASE + 0x168)           /* ENQC module configuration */
#define CSR_MQM_ENQC_SOC_STATEFUL_DB_MAP_HID_REG (CSR_MQM_ENQC_BASE + 0x16C) /* soc stateful db map host id */
#define CSR_MQM_ENQC_ENQC_IN_FIFO_GAP_REG (CSR_MQM_ENQC_BASE + 0x170) /* MQM input interface backpress threshold cfg \
                                                                       */
#define CSR_MQM_ENQC_ENQC_EQM_PT_FIFO_GAP_REG \
    (CSR_MQM_ENQC_BASE + 0x174) /* MQM passthrough fifo and eqm enq fifo backpress threshold cfg */
#define CSR_MQM_ENQC_ENQC_MRF_FIFO_BP_TH_REG \
    (CSR_MQM_ENQC_BASE + 0x178) /* MRF FIFO backpress threshold configuration */
#define CSR_MQM_ENQC_ENQC_DURF_FIFO_BP_TH_REG \
    (CSR_MQM_ENQC_BASE + 0x17C)                                       /* DURF FIFO backpress threshold configuration */
#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT0_REG (CSR_MQM_ENQC_BASE + 0x180) /* WRR weight configuration for SM/Tile/CPI */
#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT1_REG (CSR_MQM_ENQC_BASE + 0x184) /* WRR weight configuration */
#define CSR_MQM_ENQC_ENQC_RX_DU_LEN_CLR_REG (CSR_MQM_ENQC_BASE + 0x188)     /* Clr ENQC rx du length cnt */
#define CSR_MQM_ENQC_ENQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_ENQC_BASE + 0x18C) /* ENQC RAM ECC BYPASS ctrl en */
#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_ENQC_BASE + 0x190) /* ENQC RAM ctrl bus cfg reg0 */
#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_ENQC_BASE + 0x194) /* ENQC RAM ctrl bus cfg reg1 */
#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_ENQC_BASE + 0x198) /* ENQC RAM ctrl bus cfg reg2 */
#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_ENQC_BASE + 0x19C) /* ENQC RAM ctrl bus cfg reg3 */
#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_ENQC_BASE + 0x1A0) /* ENQC RAM ctrl bus cfg reg4 */
#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x1A4) /* HOST L2NIC CMQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_SOC_LNIC_SQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x1A8) /* SOC L2NIC SQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_SOC_LNIC_RQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x1AC) /* SOC L2NIC RQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_SOC_CMQ_CNT_BADDR_REG \
    (CSR_MQM_ENQC_BASE + 0x1B0) /* SOC L2NIC CMQ PI store base address in pi store space */
#define CSR_MQM_ENQC_ENQC_SOC_DB_CNT_LIMIT_REG \
    (CSR_MQM_ENQC_BASE + 0x1B4) /* SOC L2NIC SQ/RQ/CMQ PI store limite in pi store space */
#define CSR_MQM_ENQC_PASS_THROUGH_CFG_REG (CSR_MQM_ENQC_BASE + 0x1B8)       /* Pass through function enable register. */
#define CSR_MQM_ENQC_ENQC_ROOT_HOST_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C0) /* HOST and Root level backpress status */
#define CSR_MQM_ENQC_ENQC_HOSTEP_INMQ_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C4) /* INMQ HOST EP level backpress status \
                                                                               */
#define CSR_MQM_ENQC_ENQC_HOSTEP_INFMQ_XON_STA_REG \
    (CSR_MQM_ENQC_BASE + 0x1C8) /* INFMQ HOST EP level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_0_REG \
    (CSR_MQM_ENQC_BASE + 0x1CC) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_1_REG \
    (CSR_MQM_ENQC_BASE + 0x1D0) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_2_REG \
    (CSR_MQM_ENQC_BASE + 0x1D4) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_3_REG \
    (CSR_MQM_ENQC_BASE + 0x1D8) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_4_REG \
    (CSR_MQM_ENQC_BASE + 0x1DC) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_5_REG \
    (CSR_MQM_ENQC_BASE + 0x1E0) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_6_REG \
    (CSR_MQM_ENQC_BASE + 0x1E4) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_7_REG \
    (CSR_MQM_ENQC_BASE + 0x1E8) /* INMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_0_REG \
    (CSR_MQM_ENQC_BASE + 0x1EC) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_1_REG \
    (CSR_MQM_ENQC_BASE + 0x1F0) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_2_REG \
    (CSR_MQM_ENQC_BASE + 0x1F4) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_3_REG \
    (CSR_MQM_ENQC_BASE + 0x1F8) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_4_REG \
    (CSR_MQM_ENQC_BASE + 0x1FC) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_5_REG \
    (CSR_MQM_ENQC_BASE + 0x200) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_6_REG \
    (CSR_MQM_ENQC_BASE + 0x204) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_7_REG \
    (CSR_MQM_ENQC_BASE + 0x208) /* INFMQ Host_EP_COS level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x20C)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x210)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x214)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x218)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x21C)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x220)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x224)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x228)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x22C)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x230)    /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x234)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x238)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x23C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x240)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x244)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x248)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x24C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x250)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x254)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x258)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x25C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x260)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x264)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x268)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x26C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x270)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x274)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x278)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x27C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x280)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x284)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x288)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x28C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x290)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x294)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x298)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x29C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x2A0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x2A4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x2A8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x2AC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x2B0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x2B4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x2B8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x2BC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x2C0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x2C4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x2C8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x2CC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x2D0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x2D4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x2D8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x2DC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x2E0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x2E4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x2E8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x2EC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x2F0)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x2F4)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x2F8)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x2FC)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x300)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x304)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x308)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x30C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x310)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x314)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x318)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x31C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x320)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x324)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x328)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x32C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x330)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x334)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x338)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x33C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x340)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x344)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x348)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x34C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x350)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x354)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x358)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x35C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x360)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x364)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x368)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x36C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x370)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x374)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x378)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x37C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x380)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x384)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x388)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x38C)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x390)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x394)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x398)   /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x39C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x3A0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x3A4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x3A8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x3AC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x3B0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x3B4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x3B8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x3BC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x3C0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x3C4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x3C8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x3CC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x3D0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x3D4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x3D8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x3DC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x3E0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x3E4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x3E8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x3EC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x3F0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x3F4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x3F8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x3FC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x400)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x404)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x408)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_128_REG (CSR_MQM_ENQC_BASE + 0x40C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_129_REG (CSR_MQM_ENQC_BASE + 0x410)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_130_REG (CSR_MQM_ENQC_BASE + 0x414)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_131_REG (CSR_MQM_ENQC_BASE + 0x418)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_132_REG (CSR_MQM_ENQC_BASE + 0x41C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_133_REG (CSR_MQM_ENQC_BASE + 0x420)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_134_REG (CSR_MQM_ENQC_BASE + 0x424)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_135_REG (CSR_MQM_ENQC_BASE + 0x428)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_136_REG (CSR_MQM_ENQC_BASE + 0x42C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_137_REG (CSR_MQM_ENQC_BASE + 0x430)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_138_REG (CSR_MQM_ENQC_BASE + 0x434)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_139_REG (CSR_MQM_ENQC_BASE + 0x438)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_140_REG (CSR_MQM_ENQC_BASE + 0x43C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_141_REG (CSR_MQM_ENQC_BASE + 0x440)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_142_REG (CSR_MQM_ENQC_BASE + 0x444)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_143_REG (CSR_MQM_ENQC_BASE + 0x448)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_144_REG (CSR_MQM_ENQC_BASE + 0x44C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_145_REG (CSR_MQM_ENQC_BASE + 0x450)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_146_REG (CSR_MQM_ENQC_BASE + 0x454)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_147_REG (CSR_MQM_ENQC_BASE + 0x458)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_148_REG (CSR_MQM_ENQC_BASE + 0x45C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_149_REG (CSR_MQM_ENQC_BASE + 0x460)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_150_REG (CSR_MQM_ENQC_BASE + 0x464)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_151_REG (CSR_MQM_ENQC_BASE + 0x468)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_152_REG (CSR_MQM_ENQC_BASE + 0x46C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_153_REG (CSR_MQM_ENQC_BASE + 0x470)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_154_REG (CSR_MQM_ENQC_BASE + 0x474)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_155_REG (CSR_MQM_ENQC_BASE + 0x478)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_156_REG (CSR_MQM_ENQC_BASE + 0x47C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_157_REG (CSR_MQM_ENQC_BASE + 0x480)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_158_REG (CSR_MQM_ENQC_BASE + 0x484)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_159_REG (CSR_MQM_ENQC_BASE + 0x488)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_160_REG (CSR_MQM_ENQC_BASE + 0x48C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_161_REG (CSR_MQM_ENQC_BASE + 0x490)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_162_REG (CSR_MQM_ENQC_BASE + 0x494)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_163_REG (CSR_MQM_ENQC_BASE + 0x498)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_164_REG (CSR_MQM_ENQC_BASE + 0x49C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_165_REG (CSR_MQM_ENQC_BASE + 0x4A0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_166_REG (CSR_MQM_ENQC_BASE + 0x4A4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_167_REG (CSR_MQM_ENQC_BASE + 0x4A8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_168_REG (CSR_MQM_ENQC_BASE + 0x4AC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_169_REG (CSR_MQM_ENQC_BASE + 0x4B0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_170_REG (CSR_MQM_ENQC_BASE + 0x4B4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_171_REG (CSR_MQM_ENQC_BASE + 0x4B8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_172_REG (CSR_MQM_ENQC_BASE + 0x4BC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_173_REG (CSR_MQM_ENQC_BASE + 0x4C0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_174_REG (CSR_MQM_ENQC_BASE + 0x4C4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_175_REG (CSR_MQM_ENQC_BASE + 0x4C8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_176_REG (CSR_MQM_ENQC_BASE + 0x4CC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_177_REG (CSR_MQM_ENQC_BASE + 0x4D0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_178_REG (CSR_MQM_ENQC_BASE + 0x4D4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_179_REG (CSR_MQM_ENQC_BASE + 0x4D8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_180_REG (CSR_MQM_ENQC_BASE + 0x4DC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_181_REG (CSR_MQM_ENQC_BASE + 0x4E0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_182_REG (CSR_MQM_ENQC_BASE + 0x4E4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_183_REG (CSR_MQM_ENQC_BASE + 0x4E8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_184_REG (CSR_MQM_ENQC_BASE + 0x4EC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_185_REG (CSR_MQM_ENQC_BASE + 0x4F0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_186_REG (CSR_MQM_ENQC_BASE + 0x4F4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_187_REG (CSR_MQM_ENQC_BASE + 0x4F8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_188_REG (CSR_MQM_ENQC_BASE + 0x4FC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_189_REG (CSR_MQM_ENQC_BASE + 0x500)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_190_REG (CSR_MQM_ENQC_BASE + 0x504)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_191_REG (CSR_MQM_ENQC_BASE + 0x508)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_192_REG (CSR_MQM_ENQC_BASE + 0x50C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_193_REG (CSR_MQM_ENQC_BASE + 0x510)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_194_REG (CSR_MQM_ENQC_BASE + 0x514)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_195_REG (CSR_MQM_ENQC_BASE + 0x518)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_196_REG (CSR_MQM_ENQC_BASE + 0x51C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_197_REG (CSR_MQM_ENQC_BASE + 0x520)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_198_REG (CSR_MQM_ENQC_BASE + 0x524)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_199_REG (CSR_MQM_ENQC_BASE + 0x528)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_200_REG (CSR_MQM_ENQC_BASE + 0x52C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_201_REG (CSR_MQM_ENQC_BASE + 0x530)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_202_REG (CSR_MQM_ENQC_BASE + 0x534)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_203_REG (CSR_MQM_ENQC_BASE + 0x538)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_204_REG (CSR_MQM_ENQC_BASE + 0x53C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_205_REG (CSR_MQM_ENQC_BASE + 0x540)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_206_REG (CSR_MQM_ENQC_BASE + 0x544)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_207_REG (CSR_MQM_ENQC_BASE + 0x548)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_208_REG (CSR_MQM_ENQC_BASE + 0x54C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_209_REG (CSR_MQM_ENQC_BASE + 0x550)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_210_REG (CSR_MQM_ENQC_BASE + 0x554)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_211_REG (CSR_MQM_ENQC_BASE + 0x558)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_212_REG (CSR_MQM_ENQC_BASE + 0x55C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_213_REG (CSR_MQM_ENQC_BASE + 0x560)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_214_REG (CSR_MQM_ENQC_BASE + 0x564)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_215_REG (CSR_MQM_ENQC_BASE + 0x568)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_216_REG (CSR_MQM_ENQC_BASE + 0x56C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_217_REG (CSR_MQM_ENQC_BASE + 0x570)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_218_REG (CSR_MQM_ENQC_BASE + 0x574)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_219_REG (CSR_MQM_ENQC_BASE + 0x578)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_220_REG (CSR_MQM_ENQC_BASE + 0x57C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_221_REG (CSR_MQM_ENQC_BASE + 0x580)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_222_REG (CSR_MQM_ENQC_BASE + 0x584)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_223_REG (CSR_MQM_ENQC_BASE + 0x588)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_224_REG (CSR_MQM_ENQC_BASE + 0x58C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_225_REG (CSR_MQM_ENQC_BASE + 0x590)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_226_REG (CSR_MQM_ENQC_BASE + 0x594)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_227_REG (CSR_MQM_ENQC_BASE + 0x598)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_228_REG (CSR_MQM_ENQC_BASE + 0x59C)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_229_REG (CSR_MQM_ENQC_BASE + 0x5A0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_230_REG (CSR_MQM_ENQC_BASE + 0x5A4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_231_REG (CSR_MQM_ENQC_BASE + 0x5A8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_232_REG (CSR_MQM_ENQC_BASE + 0x5AC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_233_REG (CSR_MQM_ENQC_BASE + 0x5B0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_234_REG (CSR_MQM_ENQC_BASE + 0x5B4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_235_REG (CSR_MQM_ENQC_BASE + 0x5B8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_236_REG (CSR_MQM_ENQC_BASE + 0x5BC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_237_REG (CSR_MQM_ENQC_BASE + 0x5C0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_238_REG (CSR_MQM_ENQC_BASE + 0x5C4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_239_REG (CSR_MQM_ENQC_BASE + 0x5C8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_240_REG (CSR_MQM_ENQC_BASE + 0x5CC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_241_REG (CSR_MQM_ENQC_BASE + 0x5D0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_242_REG (CSR_MQM_ENQC_BASE + 0x5D4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_243_REG (CSR_MQM_ENQC_BASE + 0x5D8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_244_REG (CSR_MQM_ENQC_BASE + 0x5DC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_245_REG (CSR_MQM_ENQC_BASE + 0x5E0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_246_REG (CSR_MQM_ENQC_BASE + 0x5E4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_247_REG (CSR_MQM_ENQC_BASE + 0x5E8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_248_REG (CSR_MQM_ENQC_BASE + 0x5EC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_249_REG (CSR_MQM_ENQC_BASE + 0x5F0)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_250_REG (CSR_MQM_ENQC_BASE + 0x5F4)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_251_REG (CSR_MQM_ENQC_BASE + 0x5F8)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_252_REG (CSR_MQM_ENQC_BASE + 0x5FC)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_253_REG (CSR_MQM_ENQC_BASE + 0x600)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_254_REG (CSR_MQM_ENQC_BASE + 0x604)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_255_REG (CSR_MQM_ENQC_BASE + 0x608)  /* INMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x60C)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x610)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x614)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x618)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x61C)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x620)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x624)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x628)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x62C)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x630)   /* INFMQ Queue level backpress status */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x634)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x638)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x63C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x640)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x644)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x648)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x64C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x650)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x654)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x658)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x65C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x660)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x664)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x668)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x66C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x670)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x674)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x678)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x67C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x680)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x684)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x688)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x68C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x690)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x694)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x698)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x69C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x6A0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x6A4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x6A8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x6AC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x6B0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x6B4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x6B8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x6BC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x6C0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x6C4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x6C8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x6CC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x6D0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x6D4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x6D8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x6DC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x6E0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x6E4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x6E8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x6EC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x6F0)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x6F4)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x6F8)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x6FC)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x700)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x704)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x708)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x70C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x710)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x714)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x718)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x71C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x720)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x724)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x728)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x72C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x730)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x734)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x738)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x73C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x740)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x744)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x748)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x74C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x750)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x754)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x758)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x75C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x760)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x764)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x768)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x76C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x770)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x774)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x778)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x77C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x780)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x784)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x788)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x78C)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x790)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x794)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x798)  /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x79C) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x7A0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x7A4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x7A8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x7AC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x7B0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x7B4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x7B8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x7BC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x7C0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x7C4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x7C8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x7CC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x7D0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x7D4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x7D8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x7DC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x7E0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x7E4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x7E8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x7EC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x7F0) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x7F4) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x7F8) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x7FC) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x800) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x804) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x808) /* INFMQ Queue level backpress status \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_FLUSH_QF_EMQCNT_DONE_REG (CSR_MQM_ENQC_BASE + 0x80C)  /* enqc flush qf done and emq cnt done \
                                                                                 */
#define CSR_MQM_ENQC_ENQC_ECC_1BIT_ERR_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x810) /* statistics counter of ENQC memory ECC 1bit ERR */
#define CSR_MQM_ENQC_ENQC_ECC_2BIT_ERR_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x814) /* statistics counter of ENQC memory ECC 2bit ERR */
#define CSR_MQM_ENQC_ENQC_RX_DU_PACKET_REG \
    (CSR_MQM_ENQC_BASE + 0x830) /* statistics of the number of delay-update packet received by mqm */
#define CSR_MQM_ENQC_ENQC_RX_DU_LENGTH_REG \
    (CSR_MQM_ENQC_BASE + 0x834) /* statistics of the length that delay-update packet received by MQM */
#define CSR_MQM_ENQC_CPI_IN_EMQCNT_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x838) /* the status of cpi input fifo */
#define CSR_MQM_ENQC_SM_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x83C)         /* the status of sm input fifo */
#define CSR_MQM_ENQC_TILE_QU_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x840)  /* the status of tile and qu input fifo */
#define CSR_MQM_ENQC_ENQC_MRF_DU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x844) /* the status of message receive fifo */
#define CSR_MQM_ENQC_ENQC_PASSTHRU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x848) /* enqc passthrough fifo status */
#define CSR_MQM_ENQC_ENQC_INPUT_BP_REG (CSR_MQM_ENQC_BASE + 0x84C)   /* the backpress enqc to cpi doorbell interface */
#define CSR_MQM_ENQC_ENQC_EQM_QD_CNT_REG (CSR_MQM_ENQC_BASE + 0x850) /* EQM QD cnt */
#define CSR_MQM_ENQC_ENQC_RX_CPI_PKT_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x854) /* statistics of the number of doorbell receive from CPI */
#define CSR_MQM_ENQC_ENQC_RX_SM_PKT_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x858) /* statistics of the number of doorbell receive from SM */
#define CSR_MQM_ENQC_ENQC_RX_TILE_PKT_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x85C) /* statistics of the number of doorbell receive from Tile */
#define CSR_MQM_ENQC_ENQC_RX_QU_PKT_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x860) /* statistics of the number of doorbell receive from QU */
#define CSR_MQM_ENQC_ENQC_DIS_CPI_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x864) /* statistics of the number of doorbell discard by mqm which come from CPI */
#define CSR_MQM_ENQC_ENQC_RX_RING_ERR_DB_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x868) /* statistics of the number of doorbell which is ring error */
#define CSR_MQM_ENQC_ENQC_ENQ_IQM_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x86C) /* statistics of the number of doobell en-queue to IQM */
#define CSR_MQM_ENQC_ENQC_ENQ_EQM_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x870) /* statistics of the number of doorbell en-queue to EQM */
#define CSR_MQM_ENQC_ENQC_FILTERD_DB_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x874) /* statistics of the number of doorbell which is filterd by queue filter function */
#define CSR_MQM_ENQC_ENQC_RX_SM_CP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x878)  /* enqc rx sm cp sge comp crdt cnt */
#define CSR_MQM_ENQC_ENQC_RX_SM_DP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x87C)  /* enqc rx sm dp sge comp crdt cnt */
#define CSR_MQM_ENQC_ENQC_RX_SM_CP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x880) /* enqc rx sm cp comp data crdt cnt */
#define CSR_MQM_ENQC_ENQC_RX_SM_DP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x884) /* enqc rx sm dp comp data crdt cnt */
#define CSR_MQM_ENQC_ENQC_RX_DP_NOFL_DB_REG (CSR_MQM_ENQC_BASE + 0x888)      /* enqc rx dp nonfilter db cnt */
#define CSR_MQM_ENQC_DB_OVFL_VF_RANGE_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x88C) /* Statics the number of doorbell's txqid overflow range of VF */
#define CSR_MQM_ENQC_NONF_DB_NUM_OVFL_THR_CNT_REG \
    (CSR_MQM_ENQC_BASE + 0x890) /* Statics the number of non-filter doorbell overflow threshold of VF */
#define CSR_MQM_ENQC_MQM_ERR_TYP_DB_CNT_REG (CSR_MQM_ENQC_BASE + 0x894) /* Static the number of error type doorbell */
#define CSR_MQM_ENQC_PASS_THROUGH_STA_REG (CSR_MQM_ENQC_BASE + 0x898)   /* Pass through function status register. */

/* MQM_BRM Base address of Module's Register */
#define CSR_MQM_BRM_BASE (0x6000)

/* **************************************************************************** */
/*                      MQM_BRM Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_BRM_BRM_RW_RSV0_REG (CSR_MQM_BRM_BASE + 0x0)          /* brm rw reserved register 0 */
#define CSR_MQM_BRM_BRM_RW_RSV1_REG (CSR_MQM_BRM_BASE + 0x4)          /* brm rw reserved register 1 */
#define CSR_MQM_BRM_BRM_RW_RSV2_REG (CSR_MQM_BRM_BASE + 0x8)          /* brm rw reserved register 2 */
#define CSR_MQM_BRM_BRM_RW_RSV3_REG (CSR_MQM_BRM_BASE + 0xC)          /* brm rw reserved register 3 */
#define CSR_MQM_BRM_BRM_INDRECT_CTRL_REG (CSR_MQM_BRM_BASE + 0x10)    /* BRM Indirect access ctrl Register。 */
#define CSR_MQM_BRM_BRM_INDRECT_TIMEOUT_REG (CSR_MQM_BRM_BASE + 0x14) /* BRM Indirect Access Timeout Register。 */
#define CSR_MQM_BRM_BRM_INDRECT_DATA_0_REG (CSR_MQM_BRM_BASE + 0x18)  /* BRM Indirect Access Data Register0 */
#define CSR_MQM_BRM_BRM_INDRECT_DATA_1_REG (CSR_MQM_BRM_BASE + 0x1C)  /* BRM Indirect Access Data Register1 */
#define CSR_MQM_BRM_BRM_INT_VECTOR_REG (CSR_MQM_BRM_BASE + 0x20)      /* brm int vector */
#define CSR_MQM_BRM_BRM_INT_REG (CSR_MQM_BRM_BASE + 0x24)             /* brm int */
#define CSR_MQM_BRM_BRM_INT_EN_REG (CSR_MQM_BRM_BASE + 0x28)          /* brm int enable */
#define CSR_MQM_BRM_BRM_MEM_ECC0_REG (CSR_MQM_BRM_BASE + 0x2C)        /* RAM ECC ONE BIT ERR */
#define CSR_MQM_BRM_BRM_MEM_ECC1_REG (CSR_MQM_BRM_BASE + 0x30)        /* RAM ECC TWO BIT ERR */
#define CSR_MQM_BRM_BRM_DB_FLT_ADDR_OVFL_INT_REG \
    (CSR_MQM_BRM_BASE + 0x34)                                           /* BRM Doorbell Fliter Address Overflow Int */
#define CSR_MQM_BRM_BRM_CNT_ADDR_OVFL_INT_REG (CSR_MQM_BRM_BASE + 0x38) /* BRM PI Store Address Overflow cfg Int */
#define CSR_MQM_BRM_BRM_ATT_CNT_MEM_ECC_REQ_REG \
    (CSR_MQM_BRM_BASE + 0x50) /* BRM PI/ATT memory ecc insert request Register */
#define CSR_MQM_BRM_BRM_QF_QD_MEM_ECC_REQ_REG \
    (CSR_MQM_BRM_BASE + 0x54) /* BRM QF/QD memory ecc insert request Register */
#define CSR_MQM_BRM_BRM_QUE_FILT_SPA_REG \
    (CSR_MQM_BRM_BASE + 0x80) /* the space of queue filter and  queue description cfg */
#define CSR_MQM_BRM_BRM_ATT_SIZE_REG \
    (CSR_MQM_BRM_BASE + 0x84) /* the space of GPA address translation and PI store space cfg */
#define CSR_MQM_BRM_BRM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_BRM_BASE + 0x88) /* BRM RAM ECC BYPASS ctrl en */
#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_BRM_BASE + 0x8C) /* BRM RAM ctrl bus cfg reg0 */
#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_BRM_BASE + 0x90) /* BRM RAM ctrl bus cfg reg1 */
#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_BRM_BASE + 0x94) /* BRM RAM ctrl bus cfg reg2 */
#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_BRM_BASE + 0x98) /* BRM RAM ctrl bus cfg reg3 */
#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_BRM_BASE + 0x9C) /* BRM RAM ctrl bus cfg reg4 */
#define CSR_MQM_BRM_BRM_ECC_1BIT_ERR_CNT_REG \
    (CSR_MQM_BRM_BASE + 0xB0) /* statistics counter of BRM memory ECC 1bit ERR */
#define CSR_MQM_BRM_BRM_ECC_2BIT_ERR_CNT_REG \
    (CSR_MQM_BRM_BASE + 0xB4) /* statistics counter of BRM memory ECC 2bit ERR */

/* MQM_IQM Base address of Module's Register */
#define CSR_MQM_IQM_BASE (0x8000)

/* **************************************************************************** */
/*                      MQM_IQM Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_IQM_IQM_RW_RSV0_REG (CSR_MQM_IQM_BASE + 0x0)            /* iqm rw reserved register 0 */
#define CSR_MQM_IQM_IQM_RW_RSV1_REG (CSR_MQM_IQM_BASE + 0x4)            /* iqm rw reserved register 1 */
#define CSR_MQM_IQM_IQM_RW_RSV2_REG (CSR_MQM_IQM_BASE + 0x8)            /* iqm rw reserved register 2 */
#define CSR_MQM_IQM_IQM_RW_RSV3_REG (CSR_MQM_IQM_BASE + 0xC)            /* iqm rw reserved register 3 */
#define CSR_MQM_IQM_IQM_INDRECT_CTRL_REG (CSR_MQM_IQM_BASE + 0x10)      /* IQM Indirect access ctrl Register。 */
#define CSR_MQM_IQM_IQM_INDRECT_TIMEOUT_REG (CSR_MQM_IQM_BASE + 0x14)   /* IQM Indirect Access Timeout Register。 */
#define CSR_MQM_IQM_IQM_INDRECT_DATA_0_REG (CSR_MQM_IQM_BASE + 0x18)    /* IQM Indirect Access Data Register0 */
#define CSR_MQM_IQM_IQM_INDRECT_DATA_1_REG (CSR_MQM_IQM_BASE + 0x1C)    /* IQM Indirect Access Data Register1 */
#define CSR_MQM_IQM_IQM_INT_VECTOR_REG (CSR_MQM_IQM_BASE + 0x20)        /* iqm int vector */
#define CSR_MQM_IQM_IQM_INT_REG (CSR_MQM_IQM_BASE + 0x24)               /* iqm int */
#define CSR_MQM_IQM_IQM_INT_EN_REG (CSR_MQM_IQM_BASE + 0x28)            /* iqm int enable */
#define CSR_MQM_IQM_IQM_MEM_ECC0_REG (CSR_MQM_IQM_BASE + 0x2C)          /* RAM ECC ONE BIT ERR */
#define CSR_MQM_IQM_IQM_MEM_ECC1_REG (CSR_MQM_IQM_BASE + 0x30)          /* RAM ECC TWO BIT ERR */
#define CSR_MQM_IQM_IQM_AGING_INT_REG (CSR_MQM_IQM_BASE + 0x34)         /* iqm aging int */
#define CSR_MQM_IQM_IQM_CMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x38) /* iqm cmq link list deq emtpy int */
#define CSR_MQM_IQM_IQM_FIFO_WR_OVFL_INT_REG (CSR_MQM_IQM_BASE + 0x3C)  /* iqm fifo write overflow int */
#define CSR_MQM_IQM_IQM_FIFO_RD_UDFL_INT_REG (CSR_MQM_IQM_BASE + 0x40)  /* iqm fifo read underflow int */
#define CSR_MQM_IQM_IQM_FREE_RSC_BMP_OVERFLOW_INT_REG \
    (CSR_MQM_IQM_BASE + 0x44)                                            /* iqm free resource bitmap ovfl int err */
#define CSR_MQM_IQM_IQM_CLL_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x48)  /* iqm nmq/nfmq chunk link list deq emtpy int \
                                                                          */
#define CSR_MQM_IQM_IQM_UXMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x4C) /* iqm unmq or ucmq link list deq empty int \
                                                                          */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ1_REG (CSR_MQM_IQM_BASE + 0x50)      /* IQM FIFO INT REQ1 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ2_REG (CSR_MQM_IQM_BASE + 0x54)      /* IQM FIFO INT REQ2 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ3_REG (CSR_MQM_IQM_BASE + 0x58)      /* IQM FIFO INT REQ3 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ4_REG (CSR_MQM_IQM_BASE + 0x5C)      /* IQM FIFO INT REQ4 */
#define CSR_MQM_IQM_IQM_MEM_ECC_REQ0_REG (CSR_MQM_IQM_BASE + 0x60)       /* IQM memory ecc insert request Register0 */
#define CSR_MQM_IQM_IQM_MEM_ECC_REQ1_REG (CSR_MQM_IQM_BASE + 0x64)       /* IQM memory ecc insert request Register1 */
#define CSR_MQM_IQM_IQM_UNCRT_INT_EN_REG (CSR_MQM_IQM_BASE + 0x68)       /* IQM uncorect int mask */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ5_REG (CSR_MQM_IQM_BASE + 0x6C)      /* IQM FIFO INT REQ5 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ6_REG (CSR_MQM_IQM_BASE + 0x70)      /* IQM FIFO INT REQ6 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ7_REG (CSR_MQM_IQM_BASE + 0x74)      /* IQM FIFO INT REQ7 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ8_REG (CSR_MQM_IQM_BASE + 0x78)      /* IQM FIFO INT REQ8 */
#define CSR_MQM_IQM_IQM_FIFO_INT_REQ9_REG (CSR_MQM_IQM_BASE + 0x7C)      /* IQM FIFO INT REQ9 */
#define CSR_MQM_IQM_IQM_CHUNK_REG (CSR_MQM_IQM_BASE + 0x80)              /* chunk configuration register */
#define CSR_MQM_IQM_IQM_OUT_FIFO_TH_GAP_REG (CSR_MQM_IQM_BASE + 0x84)    /* IQM fifo threshold configuration */
#define CSR_MQM_IQM_IQM_ENQ_FIFO_AFUL_GAP_REG \
    (CSR_MQM_IQM_BASE + 0x88) /* IQM en-queue almost full threshold config register */
#define CSR_MQM_IQM_IQM_CRDT_COMP_FIFO_GAP_CFG_REG (CSR_MQM_IQM_BASE + 0x8C) /* iqm credit comp fifo gap */
#define CSR_MQM_IQM_IQM_AGING_CFG_REG (CSR_MQM_IQM_BASE + 0x90)              /* aging configuration register */
#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG0_REG (CSR_MQM_IQM_BASE + 0x94) /* IQM designate Queue De-queue cfg register */
#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG1_REG (CSR_MQM_IQM_BASE + 0x98) /* IQM designate queue De-queue vld and VF ID \
                                                                        */
#define CSR_MQM_IQM_IQM_ROOT_THR_CFG_REG \
    (CSR_MQM_IQM_BASE + 0x9C) /* the static threshold for root level config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_ROOT_HTHR_CFG_REG \
    (CSR_MQM_IQM_BASE + 0xA0) /* the high threshold offset parameter for root config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_ROOT_THR_CFG_REG \
    (CSR_MQM_IQM_BASE + 0xA4) /* the static threshold of root level nmq config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_ROOT_THR_CFG_REG \
    (CSR_MQM_IQM_BASE + 0xA8) /* the static threshold of root level nfmq config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HOST0_TH_REG \
    (CSR_MQM_IQM_BASE + 0xAC) /* the static threshold of nmq host0 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HOST1_TH_REG \
    (CSR_MQM_IQM_BASE + 0xB0) /* the static threshold of nmq host1 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HOST2_TH_REG \
    (CSR_MQM_IQM_BASE + 0xB4) /* the static threshold of nmq host2 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HOST3_TH_REG \
    (CSR_MQM_IQM_BASE + 0xB8) /* the static threshold of nmq host3 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HOST_HTH_PA_REG \
    (CSR_MQM_IQM_BASE + 0xBC) /* the nmq high threshold offset parameter config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HOST0_TH_REG \
    (CSR_MQM_IQM_BASE + 0xC0) /* the static threshold of nfmq host0 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HOST1_TH_REG \
    (CSR_MQM_IQM_BASE + 0xC4) /* the static threshold of nfmq host1 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HOST2_TH_REG \
    (CSR_MQM_IQM_BASE + 0xC8) /* the static threshold of nfmq host2 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HOST3_TH_REG \
    (CSR_MQM_IQM_BASE + 0xCC) /* the static threshold of nfmq host3 config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HOST_HTH_PA_REG \
    (CSR_MQM_IQM_BASE + 0xD0) /* the nfmq high threshold offset parameter config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_0_REG \
    (CSR_MQM_IQM_BASE + 0xD4) /* host_ep nmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_1_REG \
    (CSR_MQM_IQM_BASE + 0xD8) /* host_ep nmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_2_REG \
    (CSR_MQM_IQM_BASE + 0xDC) /* host_ep nmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_3_REG \
    (CSR_MQM_IQM_BASE + 0xE0) /* host_ep nmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_0_REG \
    (CSR_MQM_IQM_BASE + 0xE4) /* host_ep nfmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_1_REG \
    (CSR_MQM_IQM_BASE + 0xE8) /* host_ep nfmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_2_REG \
    (CSR_MQM_IQM_BASE + 0xEC) /* host_ep nfmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_3_REG \
    (CSR_MQM_IQM_BASE + 0xF0) /* host_ep nfmq profile mapping number config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_0_REG \
    (CSR_MQM_IQM_BASE + 0xF4) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_1_REG \
    (CSR_MQM_IQM_BASE + 0xF8) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_2_REG \
    (CSR_MQM_IQM_BASE + 0xFC) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_3_REG \
    (CSR_MQM_IQM_BASE + 0x100) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_4_REG \
    (CSR_MQM_IQM_BASE + 0x104) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_5_REG \
    (CSR_MQM_IQM_BASE + 0x108) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_6_REG \
    (CSR_MQM_IQM_BASE + 0x10C) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_7_REG \
    (CSR_MQM_IQM_BASE + 0x110) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_8_REG \
    (CSR_MQM_IQM_BASE + 0x114) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_9_REG \
    (CSR_MQM_IQM_BASE + 0x118) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_10_REG \
    (CSR_MQM_IQM_BASE + 0x11C) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_11_REG \
    (CSR_MQM_IQM_BASE + 0x120) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_12_REG \
    (CSR_MQM_IQM_BASE + 0x124) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_13_REG \
    (CSR_MQM_IQM_BASE + 0x128) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_14_REG \
    (CSR_MQM_IQM_BASE + 0x12C) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_TH_PRO_15_REG \
    (CSR_MQM_IQM_BASE + 0x130) /* host_ep threshold profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_0_REG \
    (CSR_MQM_IQM_BASE + 0x134) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_1_REG \
    (CSR_MQM_IQM_BASE + 0x138) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_2_REG \
    (CSR_MQM_IQM_BASE + 0x13C) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_3_REG \
    (CSR_MQM_IQM_BASE + 0x140) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_4_REG \
    (CSR_MQM_IQM_BASE + 0x144) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_5_REG \
    (CSR_MQM_IQM_BASE + 0x148) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_6_REG \
    (CSR_MQM_IQM_BASE + 0x14C) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_7_REG \
    (CSR_MQM_IQM_BASE + 0x150) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_8_REG \
    (CSR_MQM_IQM_BASE + 0x154) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_9_REG \
    (CSR_MQM_IQM_BASE + 0x158) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_10_REG \
    (CSR_MQM_IQM_BASE + 0x15C) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_11_REG \
    (CSR_MQM_IQM_BASE + 0x160) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_12_REG \
    (CSR_MQM_IQM_BASE + 0x164) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_13_REG \
    (CSR_MQM_IQM_BASE + 0x168) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_14_REG \
    (CSR_MQM_IQM_BASE + 0x16C) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HE_FAC_PRO_15_REG \
    (CSR_MQM_IQM_BASE + 0x170) /* host_ep factor and parameter profile config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_QTSS_CFG_REG \
    (CSR_MQM_IQM_BASE + 0x174) /* queue level share space config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HETSS_CFG_REG \
    (CSR_MQM_IQM_BASE + 0x178) /* host_ep level share space config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_HECTSS_CFG_REG \
    (CSR_MQM_IQM_BASE + 0x17C) /* host_ep_cos level share space config register for flow_ctrl */
#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_0_REG \
    (CSR_MQM_IQM_BASE + 0x180) /* the host level static credit threshold for sm */
#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_1_REG \
    (CSR_MQM_IQM_BASE + 0x184) /* the host level static credit threshold for sm */
#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_2_REG \
    (CSR_MQM_IQM_BASE + 0x188) /* the host level static credit threshold for sm */
#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_3_REG \
    (CSR_MQM_IQM_BASE + 0x18C) /* the host level static credit threshold for sm */
#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_4_REG \
    (CSR_MQM_IQM_BASE + 0x190) /* the host level static credit threshold for sm */
#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_DATA_REG \
    (CSR_MQM_IQM_BASE + 0x194) /* the total share data ep credit space of sm */
#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_SGE_REG \
    (CSR_MQM_IQM_BASE + 0x198)                                           /* the total share sge ep credit space of sm */
#define CSR_MQM_IQM_IQM_QU_CREDIT_TSS_CFG_REG (CSR_MQM_IQM_BASE + 0x19C) /* the total share ep credit space of qu */
#define CSR_MQM_IQM_IQM_CRR_WGT_CFG_REG (CSR_MQM_IQM_BASE + 0x1A0)       /* out to sm or qu crr weight cfg */
#define CSR_MQM_IQM_IQM_DB_MERGER_CFG_REG (CSR_MQM_IQM_BASE + 0x1A4)     /* IQM DB Merger conctrl Register */
#define CSR_MQM_IQM_SMF_DST_HASH_CFG_REG (CSR_MQM_IQM_BASE + 0x1A8)      /* SMF destination hash cfg */
#define CSR_MQM_IQM_IQM_AGING_CLR_CFG_REG (CSR_MQM_IQM_BASE + 0x1AC)     /* aging cnt and vld clr register */
#define CSR_MQM_IQM_IQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_IQM_BASE + 0x1B0) /* IQM RAM ECC BYPASS ctrl en */
#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_IQM_BASE + 0x1B4) /* IQM RAM ctrl bus cfg reg0 */
#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_IQM_BASE + 0x1B8) /* IQM RAM ctrl bus cfg reg1 */
#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_IQM_BASE + 0x1BC) /* IQM RAM ctrl bus cfg reg2 */
#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_IQM_BASE + 0x1C0) /* IQM RAM ctrl bus cfg reg3 */
#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_IQM_BASE + 0x1C4) /* IQM RAM ctrl bus cfg reg4 */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x1E0)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x1E4)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x1E8)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x1EC)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x1F0)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x1F4)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x1F8)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x1FC)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x200)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x204)  /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x208) /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x20C) /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x210) /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x214) /* iqm sm shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x218)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x21C)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x220)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x224)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x228)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x22C)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x230)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x234)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x238)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x23C)  /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x240) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x244) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x248) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x24C) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_14_REG (CSR_MQM_IQM_BASE + 0x250) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_15_REG (CSR_MQM_IQM_BASE + 0x254) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_16_REG (CSR_MQM_IQM_BASE + 0x258) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_17_REG (CSR_MQM_IQM_BASE + 0x25C) /* iqm qu shallow fifo status */
#define CSR_MQM_IQM_IQM_CMQ_CNT_REG (CSR_MQM_IQM_BASE + 0x260) /* the number of CMQ queue descriptor store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT0_REG \
    (CSR_MQM_IQM_BASE + 0x264) /* the number of queue descriptor belone to CMQ host0 and CMQ host1 store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT1_REG \
    (CSR_MQM_IQM_BASE + 0x268) /* the number of queue descriptor belone to CMQ host2 and cmq host3 store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_0_REG \
    (CSR_MQM_IQM_BASE + 0x26C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_1_REG \
    (CSR_MQM_IQM_BASE + 0x270) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_2_REG \
    (CSR_MQM_IQM_BASE + 0x274) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_3_REG \
    (CSR_MQM_IQM_BASE + 0x278) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_4_REG \
    (CSR_MQM_IQM_BASE + 0x27C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_5_REG \
    (CSR_MQM_IQM_BASE + 0x280) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_6_REG \
    (CSR_MQM_IQM_BASE + 0x284) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_7_REG \
    (CSR_MQM_IQM_BASE + 0x288) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_8_REG \
    (CSR_MQM_IQM_BASE + 0x28C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_9_REG \
    (CSR_MQM_IQM_BASE + 0x290) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_10_REG \
    (CSR_MQM_IQM_BASE + 0x294) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_11_REG \
    (CSR_MQM_IQM_BASE + 0x298) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_12_REG \
    (CSR_MQM_IQM_BASE + 0x29C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_13_REG \
    (CSR_MQM_IQM_BASE + 0x2A0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_14_REG \
    (CSR_MQM_IQM_BASE + 0x2A4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_15_REG \
    (CSR_MQM_IQM_BASE + 0x2A8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_16_REG \
    (CSR_MQM_IQM_BASE + 0x2AC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_17_REG \
    (CSR_MQM_IQM_BASE + 0x2B0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_18_REG \
    (CSR_MQM_IQM_BASE + 0x2B4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_19_REG \
    (CSR_MQM_IQM_BASE + 0x2B8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_20_REG \
    (CSR_MQM_IQM_BASE + 0x2BC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_21_REG \
    (CSR_MQM_IQM_BASE + 0x2C0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_22_REG \
    (CSR_MQM_IQM_BASE + 0x2C4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_23_REG \
    (CSR_MQM_IQM_BASE + 0x2C8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_24_REG \
    (CSR_MQM_IQM_BASE + 0x2CC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_25_REG \
    (CSR_MQM_IQM_BASE + 0x2D0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_26_REG \
    (CSR_MQM_IQM_BASE + 0x2D4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_27_REG \
    (CSR_MQM_IQM_BASE + 0x2D8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_28_REG \
    (CSR_MQM_IQM_BASE + 0x2DC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_29_REG \
    (CSR_MQM_IQM_BASE + 0x2E0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_30_REG \
    (CSR_MQM_IQM_BASE + 0x2E4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_31_REG \
    (CSR_MQM_IQM_BASE + 0x2E8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */
#define CSR_MQM_IQM_IQM_ROOTX_CNT_REG \
    (CSR_MQM_IQM_BASE + 0x2EC) /* statistics of the number of root level NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT0_REG \
    (CSR_MQM_IQM_BASE + 0x2F0) /* statistics of the number of host0 and host1 NMQ store in IQM */
#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT1_REG \
    (CSR_MQM_IQM_BASE + 0x2F4) /* statistics of the number of host2 and host3 NMQ store in IQM */
#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT0_REG \
    (CSR_MQM_IQM_BASE + 0x2F8) /* statistics of the number of host0 and host1 NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT1_REG \
    (CSR_MQM_IQM_BASE + 0x2FC) /* statistics of the number of host2 and host3 NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_0_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x300) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_1_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x304) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_2_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x308) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_3_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x30C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_4_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x310) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_5_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x314) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_6_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x318) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_7_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x31C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_8_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x320) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_9_REG \
    (CSR_MQM_IQM_BASE +                  \
        0x324) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_10_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x328) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_11_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x32C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_12_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x330) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_13_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x334) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_14_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x338) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_15_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x33C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_16_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x340) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_17_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x344) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_18_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x348) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_19_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x34C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_20_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x350) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_21_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x354) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_22_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x358) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_23_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x35C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_24_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x360) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_25_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x364) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_26_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x368) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_27_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x36C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_28_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x370) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_29_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x374) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_30_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x378) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_31_REG \
    (CSR_MQM_IQM_BASE +                   \
        0x37C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */
#define CSR_MQM_IQM_IQM_UCMQ_ROOT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0x380) /* statistics of the number of root level ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UNMQ_ROOT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0x384) /* statistics of the number of root level unmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_0_REG \
    (CSR_MQM_IQM_BASE + 0x388) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_1_REG \
    (CSR_MQM_IQM_BASE + 0x38C) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_2_REG \
    (CSR_MQM_IQM_BASE + 0x390) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_3_REG \
    (CSR_MQM_IQM_BASE + 0x394) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_4_REG \
    (CSR_MQM_IQM_BASE + 0x398) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_5_REG \
    (CSR_MQM_IQM_BASE + 0x39C) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_6_REG \
    (CSR_MQM_IQM_BASE + 0x3A0) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_7_REG \
    (CSR_MQM_IQM_BASE + 0x3A4) /* the number of unmq and ucmq for EP7~0 store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_0_REG \
    (CSR_MQM_IQM_BASE + 0x3A8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_1_REG \
    (CSR_MQM_IQM_BASE + 0x3AC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_2_REG \
    (CSR_MQM_IQM_BASE + 0x3B0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_3_REG \
    (CSR_MQM_IQM_BASE + 0x3B4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_4_REG \
    (CSR_MQM_IQM_BASE + 0x3B8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_5_REG \
    (CSR_MQM_IQM_BASE + 0x3BC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_6_REG \
    (CSR_MQM_IQM_BASE + 0x3C0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_7_REG \
    (CSR_MQM_IQM_BASE + 0x3C4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_8_REG \
    (CSR_MQM_IQM_BASE + 0x3C8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_9_REG \
    (CSR_MQM_IQM_BASE + 0x3CC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_10_REG \
    (CSR_MQM_IQM_BASE + 0x3D0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_11_REG \
    (CSR_MQM_IQM_BASE + 0x3D4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_12_REG \
    (CSR_MQM_IQM_BASE + 0x3D8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_13_REG \
    (CSR_MQM_IQM_BASE + 0x3DC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_14_REG \
    (CSR_MQM_IQM_BASE + 0x3E0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_15_REG \
    (CSR_MQM_IQM_BASE + 0x3E4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_16_REG \
    (CSR_MQM_IQM_BASE + 0x3E8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_17_REG \
    (CSR_MQM_IQM_BASE + 0x3EC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_18_REG \
    (CSR_MQM_IQM_BASE + 0x3F0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_19_REG \
    (CSR_MQM_IQM_BASE + 0x3F4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_20_REG \
    (CSR_MQM_IQM_BASE + 0x3F8) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_21_REG \
    (CSR_MQM_IQM_BASE + 0x3FC) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_22_REG \
    (CSR_MQM_IQM_BASE + 0x400) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_23_REG \
    (CSR_MQM_IQM_BASE + 0x404) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_24_REG \
    (CSR_MQM_IQM_BASE + 0x408) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_25_REG \
    (CSR_MQM_IQM_BASE + 0x40C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_26_REG \
    (CSR_MQM_IQM_BASE + 0x410) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_27_REG \
    (CSR_MQM_IQM_BASE + 0x414) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_28_REG \
    (CSR_MQM_IQM_BASE + 0x418) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_29_REG \
    (CSR_MQM_IQM_BASE + 0x41C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_30_REG \
    (CSR_MQM_IQM_BASE + 0x420) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_31_REG \
    (CSR_MQM_IQM_BASE + 0x424) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_32_REG \
    (CSR_MQM_IQM_BASE + 0x428) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_33_REG \
    (CSR_MQM_IQM_BASE + 0x42C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_34_REG \
    (CSR_MQM_IQM_BASE + 0x430) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_35_REG \
    (CSR_MQM_IQM_BASE + 0x434) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_36_REG \
    (CSR_MQM_IQM_BASE + 0x438) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_37_REG \
    (CSR_MQM_IQM_BASE + 0x43C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_38_REG \
    (CSR_MQM_IQM_BASE + 0x440) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_39_REG \
    (CSR_MQM_IQM_BASE + 0x444) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_40_REG \
    (CSR_MQM_IQM_BASE + 0x448) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_41_REG \
    (CSR_MQM_IQM_BASE + 0x44C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_42_REG \
    (CSR_MQM_IQM_BASE + 0x450) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_43_REG \
    (CSR_MQM_IQM_BASE + 0x454) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_44_REG \
    (CSR_MQM_IQM_BASE + 0x458) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_45_REG \
    (CSR_MQM_IQM_BASE + 0x45C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_46_REG \
    (CSR_MQM_IQM_BASE + 0x460) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_47_REG \
    (CSR_MQM_IQM_BASE + 0x464) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_48_REG \
    (CSR_MQM_IQM_BASE + 0x468) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_49_REG \
    (CSR_MQM_IQM_BASE + 0x46C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_50_REG \
    (CSR_MQM_IQM_BASE + 0x470) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_51_REG \
    (CSR_MQM_IQM_BASE + 0x474) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_52_REG \
    (CSR_MQM_IQM_BASE + 0x478) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_53_REG \
    (CSR_MQM_IQM_BASE + 0x47C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_54_REG \
    (CSR_MQM_IQM_BASE + 0x480) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_55_REG \
    (CSR_MQM_IQM_BASE + 0x484) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_56_REG \
    (CSR_MQM_IQM_BASE + 0x488) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_57_REG \
    (CSR_MQM_IQM_BASE + 0x48C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_58_REG \
    (CSR_MQM_IQM_BASE + 0x490) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_59_REG \
    (CSR_MQM_IQM_BASE + 0x494) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_60_REG \
    (CSR_MQM_IQM_BASE + 0x498) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_61_REG \
    (CSR_MQM_IQM_BASE + 0x49C) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_62_REG \
    (CSR_MQM_IQM_BASE + 0x4A0) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_63_REG \
    (CSR_MQM_IQM_BASE + 0x4A4) /* statistics of the number of queue level unmq or ucmq store in IQM */
#define CSR_MQM_IQM_EQM_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4A8)      /* THE STATUS OF EQM EN_QUEUE FIFO */
#define CSR_MQM_IQM_DEQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4AC)     /* THE STATUS OF DEQC EN_QUEUE FIFO */
#define CSR_MQM_IQM_IQM_ENQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4B0) /* THE STATUS OF ENQC EN_QUEUE FIFO */
#define CSR_MQM_IQM_IQM_ENQC_SOC_ENQ_FIFO_STATUS_REG \
    (CSR_MQM_IQM_BASE + 0x4B4) /* the status of enqc soc enq_queue fifo */
#define CSR_MQM_IQM_IQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_REG \
    (CSR_MQM_IQM_BASE + 0x4B8) /* iqm cpi sge credit comp fifo status */
#define CSR_MQM_IQM_IQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_REG \
    (CSR_MQM_IQM_BASE + 0x4BC) /* iqm cpi data credit comp fifo status */
#define CSR_MQM_IQM_IQM_SM_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C0) /* sm credit comp fifo status */
#define CSR_MQM_IQM_IQM_SM_OUT_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C4)       /* sm out fifo status */
#define CSR_MQM_IQM_IQM_QU_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C8) /* iqm qu credit comp fifo status */
#define CSR_MQM_IQM_ICLL_FREE_CNT_REG (CSR_MQM_IQM_BASE + 0x4CC)                /* report the free resource in IQM */
#define CSR_MQM_IQM_IQM_SM_TOTAL_CAM_CNT_REG (CSR_MQM_IQM_BASE + 0x4D0)         /* iqm sm total cam counter */
#define CSR_MQM_IQM_IQM_SM_HOST_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4D4)          /* iqm sm host credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_SGE_CRDT_BP_REG \
    (CSR_MQM_IQM_BASE + 0x4D8) /* iqm sm ep host dp rr sge credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_DAT_CRDT_BP_REG \
    (CSR_MQM_IQM_BASE + 0x4DC) /* iqm sm ep host dp rr data credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_SGE_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E0) /* iqm sm ep host dp sge credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_DAT_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E4) /* iqm sm ep host dp data credit bp \
                                                                                  */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E8)  /* iqm sm ep host cp rr credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_SOC_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4EC)      /* iqm sm ep soc dp/cp rr credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F0)     /* iqm sm ep host cp credit bp */
#define CSR_MQM_IQM_IQM_SM_EP_SOC_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F4)         /* iqm sm ep soc dp/cp credit bp */
#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP0_REG (CSR_MQM_IQM_BASE + 0x4F8) /* iqm qu ep dp credit resource 0-31 bp */
#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP1_REG (CSR_MQM_IQM_BASE + 0x4FC) /* iqm qu ep dp credit resource 32-63 bp */
#define CSR_MQM_IQM_IQM_QU_EP_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x500)  /* iqm qu ep cp credit bp */
#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP0_REG \
    (CSR_MQM_IQM_BASE + 0x504) /* iqm qu ep dp credit resource 0-31 rr bp */
#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP1_REG \
    (CSR_MQM_IQM_BASE + 0x508) /* iqm qu ep dp credit resource 32-63 rr bp */
#define CSR_MQM_IQM_IQM_QU_EP_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x50C) /* iqm qu ep cp credit rr bp */
#define CSR_MQM_IQM_IQM_FLUSH_ICLL_CAM_DONE_REG \
    (CSR_MQM_IQM_BASE + 0x510) /* iqm flush soc and host mq done and cam flush done */
#define CSR_MQM_IQM_IQM_AGING_NMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB38)     /* times of iqm nmq hardware aging nmq */
#define CSR_MQM_IQM_IQM_AGING_NFMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB3C)    /* times of iqm nfmq hardware aging nmq */
#define CSR_MQM_IQM_IQM_AGING_DISCARD_CNT_REG (CSR_MQM_IQM_BASE + 0xB40) /* iqm aging discard queue descriptor cnt */
#define CSR_MQM_IQM_IQM_TO_EQM_QD_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB44) /* iqm aging or designated deq to eqm queue descriptor cnt */
#define CSR_MQM_IQM_IQM_DEQ_SM_CNT_REG (CSR_MQM_IQM_BASE + 0xB48) /* statistics of the nunber de-queue to sm */
#define CSR_MQM_IQM_IQM_DEQ_QU_CNT_REG (CSR_MQM_IQM_BASE + 0xB4C) /* statistics of the nunber de-queue to qu */
#define CSR_MQM_IQM_MSC_IQM_DEQ_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB50) /* the number of de-queue operation that msc send to iqm */
#define CSR_MQM_IQM_IQM_NMQNFMQ_ENQ_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB54) /* the number of iqm en-queue operation for nmq and nfmq */
#define CSR_MQM_IQM_IQM_NMQNFMQ_DEQ_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB58) /* the number of iqm de-queue operation for nmq and nfmq */
#define CSR_MQM_IQM_IQM_CMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB5C) /* the number of iqm en-queue operation for cmq */
#define CSR_MQM_IQM_IQM_CMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB60) /* the number of iqm de-queue operation for cmq */
#define CSR_MQM_IQM_SOC_MSC_IQM_DEQ_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB64) /* the number of de-queue operation that soc msc send to iqm */
#define CSR_MQM_IQM_IQM_UNMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB68) /* the number of iqm en-queue operation for unmq \
                                                                     */
#define CSR_MQM_IQM_IQM_UNMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB6C) /* the number of iqm de-queue operation for unmq \
                                                                     */
#define CSR_MQM_IQM_IQM_UCMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB70) /* the number of iqm en-queue operation for ucmq \
                                                                     */
#define CSR_MQM_IQM_IQM_UCMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB74) /* the number of iqm de-queue operation for ucmq \
                                                                     */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_SGE_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB78) /* iqm rx cpi comp host sge credit cnt */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_DAT_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB7C) /* iqm rx cpi comp host data credit cnt */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_SGE_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB80) /* iqm rx cpi comp ep dp sge credit cnt */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_SGE_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB84) /* iqm rx cpi comp ep cp sge credit cnt */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_DAT_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB88) /* iqm rx cpi comp ep dp data credit cnt */
#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_DAT_CRDT_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB8C) /* iqm rx cpi comp ep cp data credit cnt */
#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_DP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB90) /* iqm rx qu comp ep dp credit cnt */
#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_CP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB94) /* iqm rx qu comp ep cp credit cnt */
#define CSR_MQM_IQM_IQM_ECC_1BIT_ERR_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB98) /* statistics counter of IQM memory ECC 1bit ERR */
#define CSR_MQM_IQM_IQM_ECC_2BIT_ERR_CNT_REG \
    (CSR_MQM_IQM_BASE + 0xB9C) /* statistics counter of IQM memory ECC 2bit ERR */

/* MQM_EQM Base address of Module's Register */
#define CSR_MQM_EQM_BASE (0xA000)

/* **************************************************************************** */
/*                      MQM_EQM Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_EQM_EQM_RW_RSV0_REG (CSR_MQM_EQM_BASE + 0x0)            /* EQM rw reserved 0 */
#define CSR_MQM_EQM_EQM_RW_RSV1_REG (CSR_MQM_EQM_BASE + 0x4)            /* EQM rw reserved 1 */
#define CSR_MQM_EQM_EQM_RW_RSV2_REG (CSR_MQM_EQM_BASE + 0x8)            /* EQM rw reserved 2 */
#define CSR_MQM_EQM_EQM_RW_RSV3_REG (CSR_MQM_EQM_BASE + 0xC)            /* EQM rw reserved 3 */
#define CSR_MQM_EQM_EQM_INDRECT_CTRL_REG (CSR_MQM_EQM_BASE + 0x10)      /* EQM Indirect access ctrl Register。 */
#define CSR_MQM_EQM_EQM_INDRECT_TIMEOUT_REG (CSR_MQM_EQM_BASE + 0x14)   /* EQM Indirect Access Timeout Register。 */
#define CSR_MQM_EQM_EQM_INDRECT_DATA_REG (CSR_MQM_EQM_BASE + 0x18)      /* EQM Indirect Access Data Register. */
#define CSR_MQM_EQM_EQM_ECQM_BP_BYPASS_REG (CSR_MQM_EQM_BASE + 0x1C)    /* EQM ECQM_HFIFO Backpresssure Bypass */
#define CSR_MQM_EQM_EQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_EQM_BASE + 0x20) /* EQM RAM ECC Bypass控制寄存器 */
#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_EQM_BASE + 0x24) /* EQM RAM ctrl bus cfg reg0 */
#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_EQM_BASE + 0x28) /* EQM RAM ctrl bus cfg reg1 */
#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_EQM_BASE + 0x2C) /* EQM RAM ctrl bus cfg reg2 */
#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_EQM_BASE + 0x30) /* EQM RAM ctrl bus cfg reg3 */
#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_EQM_BASE + 0x34) /* EQM RAM ctrl bus cfg reg4 */
#define CSR_MQM_EQM_EQM_INT_VECTOR_REG (CSR_MQM_EQM_BASE + 0x40)   /* EQM Internal ERR Interrupt Vector Register. */
#define CSR_MQM_EQM_EQM_INT_REG (CSR_MQM_EQM_BASE + 0x44)          /* EQM Internal ERR Interrupt Register. */
#define CSR_MQM_EQM_EQM_INT_EN_REG (CSR_MQM_EQM_BASE + 0x48)       /* EQM Internal ERR Interrupt Mask Register. */
#define CSR_MQM_EQM_EQM_MEM_ECC_REQ_REG (CSR_MQM_EQM_BASE + 0x4C)  /* EQM memory ecc insert request Register */
#define CSR_MQM_EQM_EQM_MEM_1BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x50) /* EQM 1Bit ECC Check Err Register. */
#define CSR_MQM_EQM_EQM_MEM_2BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x54) /* EQM 2Bit ECC Check Err Register. */
#define CSR_MQM_EQM_EQM_QL_DEQ_EMPTY_INT_REG \
    (CSR_MQM_EQM_BASE + 0x58) /* EQM Queue Deq Interrupt Register When Queue Empty */
#define CSR_MQM_EQM_EQM_CLL_FAP_EXHAUSTED_INT_REG \
    (CSR_MQM_EQM_BASE + 0x5C) /* EQM CHUNK Link List Interrupt Register When Free Addr Pool Resource Exhausted。 */
#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_REG \
    (CSR_MQM_EQM_BASE + 0x60) /* EQM FIFO Write Interrupt Register When Full */
#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_EN_REG \
    (CSR_MQM_EQM_BASE + 0x64) /* EQM FIFO Write Interrupt Mask Register When Full */
#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_REG \
    (CSR_MQM_EQM_BASE + 0x68) /* EQM FIFO Write Interrupt Register Whenable Full */
#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_EN_REG \
    (CSR_MQM_EQM_BASE + 0x6C) /* EQM FIFO Write Interrupt Mask Register When Full */
#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_REG \
    (CSR_MQM_EQM_BASE + 0x70) /* EQM FIFO Read Interrupt Register When Empty */
#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_EN_REG \
    (CSR_MQM_EQM_BASE + 0x74) /* EQM FIFO Read Interrupt Mask Register When Empty */
#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT_REG \
    (CSR_MQM_EQM_BASE + 0x78) /* EQM Receive E0 Interrupt Register From RING Interface */
#define CSR_MQM_EQM_EQM_BRMATT_RD_INT_REG (CSR_MQM_EQM_BASE + 0x7C) /* EQM Read ATT Error Interrupt from BRM */
#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT1_REG \
    (CSR_MQM_EQM_BASE + 0x80) /* EQM Receive E1 Interrupt Register From RING Interface */
#define CSR_MQM_EQM_EQM_UNCRT_INT_EN_REG (CSR_MQM_EQM_BASE + 0x84) /* enqc uncorrect int en */
#define CSR_MQM_EQM_EQM_DWQ_RSC_DEP_CFG_REG \
    (CSR_MQM_EQM_BASE + 0x800) /* EQM DWQ Space Addr Pool Depth config Register. */
#define CSR_MQM_EQM_EQM_PACK_CHANNEL_CFG_REG (CSR_MQM_EQM_BASE + 0x804)   /* EQM Packing Channel Config Register. */
#define CSR_MQM_EQM_EQM_DB_STORE_SPACE_SEL_REG (CSR_MQM_EQM_BASE + 0x808) /* DB溢出空间选择 */
#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG0_REG \
    (CSR_MQM_EQM_BASE + 0x80C) /* EQM HOST0~1 chunk number Config Register. */
#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG1_REG \
    (CSR_MQM_EQM_BASE + 0x810)                                       /* EQM HOST2~3 chunk number Config Register. */
#define CSR_MQM_EQM_EQM_PAGE_SIZE_CFG_REG (CSR_MQM_EQM_BASE + 0x814) /* EQM HOST MEM page size Register. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_0_REG (CSR_MQM_EQM_BASE + 0x820) /* EQM DMA Channel config Register. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_1_REG (CSR_MQM_EQM_BASE + 0x824) /* EQM DMA Channel config Register. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_2_REG (CSR_MQM_EQM_BASE + 0x828) /* EQM DMA Channel config Register. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_3_REG (CSR_MQM_EQM_BASE + 0x82C) /* EQM DMA Channel config Register. */
#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG0_REG \
    (CSR_MQM_EQM_BASE + 0x830) /* EQM HOST search the BRM(10K GPA) Base Address Config Register0 */
#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG1_REG \
    (CSR_MQM_EQM_BASE + 0x834) /* EQM HOST search the BRM(10K GPA) Base Address Config Register1 */
#define CSR_MQM_EQM_EQM_DMA_OUTSTD_NUM_REG \
    (CSR_MQM_EQM_BASE + 0x838) /* EQM Outstanding config Register for every Host */
#define CSR_MQM_EQM_EQM_HOST_DMA_OUTSTD_NUM_REG \
    (CSR_MQM_EQM_BASE + 0x83C)                                      /* EQM Outstanding config Register for every Host */
#define CSR_MQM_EQM_EQM_FIFO_GAP_CFG_REG (CSR_MQM_EQM_BASE + 0x840) /* EQM FIFO Back Press Threshold config register. \
                                                                     */
#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG0_REG \
    (CSR_MQM_EQM_BASE + 0x844) /* EQM DWQ Interface Back Press Threshold config Register. */
#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG1_REG \
    (CSR_MQM_EQM_BASE + 0x848) /* EQM DWQ Interface Back Press Threshold config Register. */
#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG2_REG \
    (CSR_MQM_EQM_BASE + 0x84C) /* EQM DWQ Interface Back Press Threshold config Register. */
#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_0_REG \
    (CSR_MQM_EQM_BASE + 0x850) /* EQM HOSTx Halt Threshold Config Register for CPI */
#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_1_REG \
    (CSR_MQM_EQM_BASE + 0x854) /* EQM HOSTx Halt Threshold Config Register for CPI */
#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_2_REG \
    (CSR_MQM_EQM_BASE + 0x858) /* EQM HOSTx Halt Threshold Config Register for CPI */
#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_3_REG \
    (CSR_MQM_EQM_BASE + 0x85C) /* EQM HOSTx Halt Threshold Config Register for CPI */
#define CSR_MQM_EQM_EQM_HOST_FIFO_DEPTH_CFG_REG (CSR_MQM_EQM_BASE + 0x860) /* EQM Host FIFO Depth Config Register */
#define CSR_MQM_EQM_EQM_DMARD_FIFO_BP_TH_REG \
    (CSR_MQM_EQM_BASE + 0x864) /* EQM DMA Read fifo Backpress threshold config register */
#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH0_REG \
    (CSR_MQM_EQM_BASE + 0x868) /* EQM DMA Read fifo Backpress threshold config register */
#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH1_REG \
    (CSR_MQM_EQM_BASE + 0x86C) /* EQM DMA Read fifo Backpress threshold config register */
#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH0_REG \
    (CSR_MQM_EQM_BASE + 0x870) /* EQM DMA Write fifo Backpress threshold config register */
#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH1_REG \
    (CSR_MQM_EQM_BASE + 0x874) /* EQM DMA Write fifo Backpress threshold config register */
#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH0_REG \
    (CSR_MQM_EQM_BASE + 0x878) /* EQM HOST0 DMA Channel FIFO Config Register */
#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH1_REG \
    (CSR_MQM_EQM_BASE + 0x87C)                                          /* EQM HOST0 DMA Channel FIFO Config Register */
#define CSR_MQM_EQM_EQM_DMACMD_RDFIFO_TH_REG (CSR_MQM_EQM_BASE + 0x880) /* EQM HOST0 DMA Channel FIFO Config Register \
                                                                         */
#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH0_REG \
    (CSR_MQM_EQM_BASE + 0x884) /* EQM HOST0 DMA Channel FIFO Config Register */
#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH1_REG \
    (CSR_MQM_EQM_BASE + 0x888) /* EQM HOST0 DMA Channel FIFO Config Register */
#define CSR_MQM_EQM_EQM_OUTSTD_FIFO_ALEMPTY_TH_REG (CSR_MQM_EQM_BASE + 0x88C) /* outstand fifo 将空水线 */
#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP0_REG (CSR_MQM_EQM_BASE + 0x890) /* EQM Host0 Host1 DMA CMD FIFO ALFUL GAP \
                                                                            */
#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP1_REG (CSR_MQM_EQM_BASE + 0x894) /* EQM Host2 Host3 DMA CMD FIFO ALFUL GAP \
                                                                            */
#define CSR_MQM_EQM_EQM_DMAWR_FIFO_BP_GAP_REG \
    (CSR_MQM_EQM_BASE + 0x898) /* EQM DMA Write fifo Backpress gap threshold config register */
#define CSR_MQM_EQM_EQM_INNER_BP_STATUS0_REG (CSR_MQM_EQM_BASE + 0x1000) /* EQM Inner backpress status Register0 */
#define CSR_MQM_EQM_EQM_INNER_BP_STATUS1_REG (CSR_MQM_EQM_BASE + 0x1004) /* EQM Inner backpress status Register1 */
#define CSR_MQM_EQM_EQM_FIFO_STATUS0_REG \
    (CSR_MQM_EQM_BASE + 0x1008) /* EQM Internal FIFO DFX Register.(including full、empty) */
#define CSR_MQM_EQM_EQM_FIFO_STATUS1_REG \
    (CSR_MQM_EQM_BASE + 0x100C) /* EQM Internal FIFO DFX Register.(including full、empty) */
#define CSR_MQM_EQM_EQM_RING_DFX_ERR_CNT_REG \
    (CSR_MQM_EQM_BASE + 0x1800)                                     /* EQM Receive E0/E1 Interrupt Count Register. */
#define CSR_MQM_EQM_EQM_SM_OVFL_CNT_REG (CSR_MQM_EQM_BASE + 0x1804) /* The redundant DoorBell number overflow form SM \
                                                                     */
#define CSR_MQM_EQM_EQM_DWQ_FREE_ADDR_CNT_REG (CSR_MQM_EQM_BASE + 0x1808)    /* EQM DWQ Free Addr Count Register. */
#define CSR_MQM_EQM_EQM_DWQ_LIST_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x180C)      /* DWQ LIST DB Count Register */
#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_0_REG (CSR_MQM_EQM_BASE + 0x1810) /* DWQ HOSTx LIST DB Count Register */
#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_1_REG (CSR_MQM_EQM_BASE + 0x1814) /* DWQ HOSTx LIST DB Count Register */
#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_2_REG (CSR_MQM_EQM_BASE + 0x1818) /* DWQ HOSTx LIST DB Count Register */
#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_3_REG (CSR_MQM_EQM_BASE + 0x181C) /* DWQ HOSTx LIST DB Count Register */
#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x1820) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */
#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x1824) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */
#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x1828) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */
#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x182C)                                    /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */
#define CSR_MQM_EQM_EQM_NMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1830) /* EQM NMQ DB Count Register. */
#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1840)  /* EQM NMQ HOSTx DB Count Register. */
#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1844)  /* EQM NMQ HOSTx DB Count Register. */
#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1848)  /* EQM NMQ HOSTx DB Count Register. */
#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x184C)  /* EQM NMQ HOSTx DB Count Register. */
#define CSR_MQM_EQM_EQM_NFMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1850)         /* EQM NFMQ DB Count Register. */
#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1860) /* EQM NFMQ HOSTx DB Count Register */
#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1864) /* EQM NFMQ HOSTx DB Count Register */
#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1868) /* EQM NFMQ HOSTx DB Count Register */
#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x186C) /* EQM NFMQ HOSTx DB Count Register */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x1870) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x1874) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x1878) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */
#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x187C) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */
#define CSR_MQM_EQM_EQM_DWQ_TILE_CNT_REG (CSR_MQM_EQM_BASE + 0x1880) /* EQM DWQ Space Count Register For TILE. */
#define CSR_MQM_EQM_EQM_DWQ_SM_CNT_REG (CSR_MQM_EQM_BASE + 0x1884)   /* EQM DWQ Space Count Register For Small-Memory. \
                                                                      */
#define CSR_MQM_EQM_EQM_DWQ_QU_CNT_REG (CSR_MQM_EQM_BASE + 0x1888)   /* EQM DWQ Space Count Register For QU. */
#define CSR_MQM_EQM_EQM_DWQ_CPI_CNT_REG (CSR_MQM_EQM_BASE + 0x188C)  /* EQM DWQ Space Count Register For CPI. */
#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x1890) /* EQM HOSTx DWQ Space Count Register For CPI. */
#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x1894) /* EQM HOSTx DWQ Space Count Register For CPI. */
#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x1898) /* EQM HOSTx DWQ Space Count Register For CPI. */
#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x189C) /* EQM HOSTx DWQ Space Count Register For CPI. */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18A0) /* ECQM发出的Hostx 入队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18A4) /* ECQM发出的Hostx 入队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18A8) /* ECQM发出的Hostx 入队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18AC) /* ECQM发出的Hostx 入队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18B0) /* ECQM发出的Hostx 出队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18B4) /* ECQM发出的Hostx 出队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18B8) /* ECQM发出的Hostx 出队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18BC) /* ECQM发出的Hostx 出队命令个数统计 \
                                                                                  */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x18C0) /* ECQM发出的Hostx 二次出队命令个数统计 */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x18C4) /* ECQM发出的Hostx 二次出队命令个数统计 */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x18C8) /* ECQM发出的Hostx 二次出队命令个数统计 */
#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x18CC) /* ECQM发出的Hostx 二次出队命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x18D0) /* DMAGen发出的Hostx 溢出命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x18D4) /* DMAGen发出的Hostx 溢出命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x18D8) /* DMAGen发出的Hostx 溢出命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x18DC) /* DMAGen发出的Hostx 溢出命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x18E0) /* DMAGen发出的Hostx 回读命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x18E4) /* DMAGen发出的Hostx 回读命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x18E8) /* DMAGen发出的Hostx 回读命令个数统计 */
#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x18EC) /* DMAGen发出的Hostx 回读命令个数统计 */
#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x18F0) /* EQM HOSTx Write DB Count Sended to RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x18F4) /* EQM HOSTx Write DB Count Sended to RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x18F8) /* EQM HOSTx Write DB Count Sended to RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x18FC) /* EQM HOSTx Write DB Count Sended to RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x1900) /* EQM HOSTx Read DB Count Recieved from RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x1904) /* EQM HOSTx Read DB Count Recieved from RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x1908) /* EQM HOSTx Read DB Count Recieved from RING. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x190C) /* EQM HOSTx Read DB Count Recieved from RING. */
#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_0_REG \
    (CSR_MQM_EQM_BASE + 0x1910) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */
#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_1_REG \
    (CSR_MQM_EQM_BASE + 0x1914) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */
#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_2_REG \
    (CSR_MQM_EQM_BASE + 0x1918) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */
#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_3_REG \
    (CSR_MQM_EQM_BASE + 0x191C) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */
#define CSR_MQM_EQM_EQM_IQM_SEND_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1920) /* EQM DB Count that be sended to IQM. */
#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_0_REG                                                            \
    (CSR_MQM_EQM_BASE + 0x1930) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \
                                   CPI,the DB information be recorded to the Count Register). */
#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_1_REG                                                            \
    (CSR_MQM_EQM_BASE + 0x1934) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \
                                   CPI,the DB information be recorded to the Count Register). */
#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_2_REG                                                            \
    (CSR_MQM_EQM_BASE + 0x1938) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \
                                   CPI,the DB information be recorded to the Count Register). */
#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_3_REG                                                            \
    (CSR_MQM_EQM_BASE + 0x193C) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \
                                   CPI,the DB information be recorded to the Count Register). */
#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX0_REG \
    (CSR_MQM_EQM_BASE + 0x1940) /* EQM Outstand Count Register for DMA Operate. */
#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX1_REG \
    (CSR_MQM_EQM_BASE + 0x1944) /* EQM Host Outstand Count Register for DMA Operate. */
#define CSR_MQM_EQM_EQM_ECC_1BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x1948) /* EQM Memory ECC 1bit count */
#define CSR_MQM_EQM_EQM_ECC_2BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x194C) /* EQM Memory ECC 2bit count */

/* MQM_MSC Base address of Module's Register */
#define CSR_MQM_MSC_BASE (0xC000)

/* **************************************************************************** */
/*                      MQM_MSC Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_MSC_MSC_RW_RSV0_REG (CSR_MQM_MSC_BASE + 0x0)               /* MSC reserved rw register. */
#define CSR_MQM_MSC_MSC_RW_RSV1_REG (CSR_MQM_MSC_BASE + 0x4)               /* MSC reserved rw register. */
#define CSR_MQM_MSC_MSC_RW_RSV2_REG (CSR_MQM_MSC_BASE + 0x8)               /* MSC reserved rw register. */
#define CSR_MQM_MSC_MSC_RW_RSV3_REG (CSR_MQM_MSC_BASE + 0xC)               /* MSC reserved rw register. */
#define CSR_MQM_MSC_MSC_INDRECT_CTRL_REG (CSR_MQM_MSC_BASE + 0x10)         /* Indirect access ctrl Register。 */
#define CSR_MQM_MSC_MSC_INDRECT_TIMEOUT_REG (CSR_MQM_MSC_BASE + 0x14)      /* Indirect Access Timeout Register。 */
#define CSR_MQM_MSC_MSC_INDRECT_DATA_0_REG (CSR_MQM_MSC_BASE + 0x18)       /* Indirect Access Data Register BIT63_32 */
#define CSR_MQM_MSC_MSC_INDRECT_DATA_1_REG (CSR_MQM_MSC_BASE + 0x1C)       /* Indirect Access Data Register BIT31_0 */
#define CSR_MQM_MSC_MSC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_MSC_BASE + 0x20)    /* RAM ECC BYPASS控制寄存器 */
#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_MSC_BASE + 0x24)    /* RAM CTRL_BUS寄存器0 */
#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_MSC_BASE + 0x28)    /* RAM CTRL_BUS寄存器1 */
#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_MSC_BASE + 0x2C)    /* RAM CTRL_BUS寄存器2 */
#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_MSC_BASE + 0x30)    /* RAM CTRL_BUS寄存器3 */
#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_MSC_BASE + 0x34)    /* RAM CTRL_BUS寄存器4 */
#define CSR_MQM_MSC_MSC_INT_VECTOR_REG (CSR_MQM_MSC_BASE + 0x100)          /* MSC ERROR INT VECTOR */
#define CSR_MQM_MSC_MSC_INT_REG (CSR_MQM_MSC_BASE + 0x104)                 /* MSC ERROR INT */
#define CSR_MQM_MSC_MSC_INT_EN_REG (CSR_MQM_MSC_BASE + 0x108)              /* MSC ERROR ENABLE */
#define CSR_MQM_MSC_MSC_MEM_ERR_REQ0_REG (CSR_MQM_MSC_BASE + 0x10C)        /* Msc mem Error Request register0. */
#define CSR_MQM_MSC_MSC_MEM_ERR_REQ1_REG (CSR_MQM_MSC_BASE + 0x110)        /* Msc mem Error Request registe1. */
#define CSR_MQM_MSC_MSC_MEM_ERR_REQ2_REG (CSR_MQM_MSC_BASE + 0x114)        /* Msc mem Error Request registe2. */
#define CSR_MQM_MSC_MSC_MEM_ERR_REQ3_REG (CSR_MQM_MSC_BASE + 0x118)        /* Msc mem Error Request registe3. */
#define CSR_MQM_MSC_MSC_MEM_ERR_REQ4_REG (CSR_MQM_MSC_BASE + 0x11C)        /* Msc mem Error Request registe4. */
#define CSR_MQM_MSC_MSC_ECC_ONE_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x120)     /* RAM ECC ONE BIT ERROR */
#define CSR_MQM_MSC_MSC_ECC_TWO_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x124)     /* RAM ECC TWO BIT ERROR */
#define CSR_MQM_MSC_MSC_MQ_BIND_INT_REG (CSR_MQM_MSC_BASE + 0x128)         /* MQ MAPPING CONFIG ERROR */
#define CSR_MQM_MSC_MSC_VNIC_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x12C)  /* VF SPCNT Interface ERROR */
#define CSR_MQM_MSC_MSC_VNIC_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x130)  /* VF SPCNT Calculation ERROR */
#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x134) /* SOCEP SPCNT Interface ERROR */
#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x138) /* SOCEP SPCNT Calculation ERROR */
#define CSR_MQM_MSC_MSC_FIFO_INT0_REG (CSR_MQM_MSC_BASE + 0x150) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT0_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x154) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT1_REG (CSR_MQM_MSC_BASE + 0x158) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT1_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x15C) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT2_REG (CSR_MQM_MSC_BASE + 0x160) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT2_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x164) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT3_REG (CSR_MQM_MSC_BASE + 0x168) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT3_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x16C) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT4_REG (CSR_MQM_MSC_BASE + 0x170) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT4_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x174) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT5_REG (CSR_MQM_MSC_BASE + 0x178) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT5_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x17C) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT6_REG (CSR_MQM_MSC_BASE + 0x180) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT6_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x184) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_FIFO_INT7_REG (CSR_MQM_MSC_BASE + 0x188) /* FIFO interrupt,include write int and read int */
#define CSR_MQM_MSC_MSC_FIFO_INT7_MASK_REG \
    (CSR_MQM_MSC_BASE + 0x18C) /* FIFO interrupt,include write int and read init mask */
#define CSR_MQM_MSC_MSC_BP_DELAY_CNT_REG (CSR_MQM_MSC_BASE + 0x200)      /* MSC EP and Cos backpress delay cnt */
#define CSR_MQM_MSC_MSC_VF_SP_CNT_EN_REG (CSR_MQM_MSC_BASE + 0x204)      /* MSC VF SP CNT EN */
#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STF_REG (CSR_MQM_MSC_BASE + 0x250)  /* Normal Service pre-subtract the pktlen */
#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STL_REG (CSR_MQM_MSC_BASE + 0x254)  /* Normal Service pre-subtract the pktlen */
#define CSR_MQM_MSC_CMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x258)  /* CMQ pre-subtract the pktlen */
#define CSR_MQM_MSC_NFMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x25C) /* NFMQ pre-subtract the pktlen */
#define CSR_MQM_MSC_PRESUB_PKTNUM_REG (CSR_MQM_MSC_BASE + 0x260)         /* MSC pre-subtract the pktnum */
#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCNMQ_REG \
    (CSR_MQM_MSC_BASE + 0x264) /* Normal Service pre-subtract the pktlen For SOCMSC */
#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCCMQ_REG \
    (CSR_MQM_MSC_BASE + 0x268) /* Command Service pre-subtract the pktlen For SOCMSC */
#define CSR_MQM_MSC_PRESUB_PKTNUM_SOC_REG (CSR_MQM_MSC_BASE + 0x26C) /* MSC pre-subtract the pktnum for SOCMSC */
#define CSR_MQM_MSC_MSC_PPS_SHAPER_CFG_PKTLEN_REG (CSR_MQM_MSC_BASE + 0x270) /* MSC Shaper Config Pktlen */
#define CSR_MQM_MSC_MSC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_MSC_BASE + 0x274)   /* MSC ROOT CRR WEIGHT Config */
#define CSR_MQM_MSC_SOCMSC_ROOT_SCH_WGT_CFG_REG (CSR_MQM_MSC_BASE + 0x278)   /* SOC MSC ROOT SCH Weight Config */
#define CSR_MQM_MSC_WEIGHT_NS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x27C)          /* Normal queue weight offset */
#define CSR_MQM_MSC_WEIGHT_CS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x280)          /* Command queue weight offset */
#define CSR_MQM_MSC_WEIGHT_MSCSOC_OFFSET_REG (CSR_MQM_MSC_BASE + 0x284)      /* SOC MSCl queue weight offset */
#define CSR_MQM_MSC_HOST_WEIGHT_NS_REG (CSR_MQM_MSC_BASE + 0x288)            /* Normal MQ host weight */
#define CSR_MQM_MSC_HOST_WEIGHT_CS_REG (CSR_MQM_MSC_BASE + 0x28C)      /* CMQ Host Node Weight Configuration Table */
#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_0_REG (CSR_MQM_MSC_BASE + 0x2F0)  /* CS QA Node Weight Configuration Table for CS \
                                                                        */
#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_1_REG (CSR_MQM_MSC_BASE + 0x2F4)  /* CS QA Node Weight Configuration Table for CS \
                                                                        */
#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_2_REG (CSR_MQM_MSC_BASE + 0x2F8)  /* CS QA Node Weight Configuration Table for CS \
                                                                        */
#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_3_REG (CSR_MQM_MSC_BASE + 0x2FC)  /* CS QA Node Weight Configuration Table for CS \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_0_REG (CSR_MQM_MSC_BASE + 0x300)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_1_REG (CSR_MQM_MSC_BASE + 0x304)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_2_REG (CSR_MQM_MSC_BASE + 0x308)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_3_REG (CSR_MQM_MSC_BASE + 0x30C)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_4_REG (CSR_MQM_MSC_BASE + 0x310)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_5_REG (CSR_MQM_MSC_BASE + 0x314)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_6_REG (CSR_MQM_MSC_BASE + 0x318)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_7_REG (CSR_MQM_MSC_BASE + 0x31C)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_8_REG (CSR_MQM_MSC_BASE + 0x320)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_9_REG (CSR_MQM_MSC_BASE + 0x324)  /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_10_REG (CSR_MQM_MSC_BASE + 0x328) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_11_REG (CSR_MQM_MSC_BASE + 0x32C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_12_REG (CSR_MQM_MSC_BASE + 0x330) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_13_REG (CSR_MQM_MSC_BASE + 0x334) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_14_REG (CSR_MQM_MSC_BASE + 0x338) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_15_REG (CSR_MQM_MSC_BASE + 0x33C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_16_REG (CSR_MQM_MSC_BASE + 0x340) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_17_REG (CSR_MQM_MSC_BASE + 0x344) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_18_REG (CSR_MQM_MSC_BASE + 0x348) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_19_REG (CSR_MQM_MSC_BASE + 0x34C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_20_REG (CSR_MQM_MSC_BASE + 0x350) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_21_REG (CSR_MQM_MSC_BASE + 0x354) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_22_REG (CSR_MQM_MSC_BASE + 0x358) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_23_REG (CSR_MQM_MSC_BASE + 0x35C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_24_REG (CSR_MQM_MSC_BASE + 0x360) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_25_REG (CSR_MQM_MSC_BASE + 0x364) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_26_REG (CSR_MQM_MSC_BASE + 0x368) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_27_REG (CSR_MQM_MSC_BASE + 0x36C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_28_REG (CSR_MQM_MSC_BASE + 0x370) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_29_REG (CSR_MQM_MSC_BASE + 0x374) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_30_REG (CSR_MQM_MSC_BASE + 0x378) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_31_REG (CSR_MQM_MSC_BASE + 0x37C) /* EP Node Weight Configuration Table for NS */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_0_REG (CSR_MQM_MSC_BASE + 0x380) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_1_REG (CSR_MQM_MSC_BASE + 0x384) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_2_REG (CSR_MQM_MSC_BASE + 0x388) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_3_REG (CSR_MQM_MSC_BASE + 0x38C) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_4_REG (CSR_MQM_MSC_BASE + 0x390) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_5_REG (CSR_MQM_MSC_BASE + 0x394) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_6_REG (CSR_MQM_MSC_BASE + 0x398) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_7_REG (CSR_MQM_MSC_BASE + 0x39C) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_8_REG (CSR_MQM_MSC_BASE + 0x3A0) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_9_REG (CSR_MQM_MSC_BASE + 0x3A4) /* EP Node Weight Configuration Table for CMQ \
                                                                        */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_10_REG (CSR_MQM_MSC_BASE + 0x3A8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_11_REG (CSR_MQM_MSC_BASE + 0x3AC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_12_REG (CSR_MQM_MSC_BASE + 0x3B0) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_13_REG (CSR_MQM_MSC_BASE + 0x3B4) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_14_REG (CSR_MQM_MSC_BASE + 0x3B8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_15_REG (CSR_MQM_MSC_BASE + 0x3BC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_16_REG (CSR_MQM_MSC_BASE + 0x3C0) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_17_REG (CSR_MQM_MSC_BASE + 0x3C4) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_18_REG (CSR_MQM_MSC_BASE + 0x3C8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_19_REG (CSR_MQM_MSC_BASE + 0x3CC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_20_REG (CSR_MQM_MSC_BASE + 0x3D0) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_21_REG (CSR_MQM_MSC_BASE + 0x3D4) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_22_REG (CSR_MQM_MSC_BASE + 0x3D8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_23_REG (CSR_MQM_MSC_BASE + 0x3DC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_24_REG (CSR_MQM_MSC_BASE + 0x3E0) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_25_REG (CSR_MQM_MSC_BASE + 0x3E4) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_26_REG (CSR_MQM_MSC_BASE + 0x3E8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_27_REG (CSR_MQM_MSC_BASE + 0x3EC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_28_REG (CSR_MQM_MSC_BASE + 0x3F0) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_29_REG (CSR_MQM_MSC_BASE + 0x3F4) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_30_REG (CSR_MQM_MSC_BASE + 0x3F8) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_31_REG (CSR_MQM_MSC_BASE + 0x3FC) /* EP Node Weight Configuration Table for CMQ \
                                                                         */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_0_REG \
    (CSR_MQM_MSC_BASE + 0x400) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_1_REG \
    (CSR_MQM_MSC_BASE + 0x404) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_2_REG \
    (CSR_MQM_MSC_BASE + 0x408) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_3_REG \
    (CSR_MQM_MSC_BASE + 0x40C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_4_REG \
    (CSR_MQM_MSC_BASE + 0x410) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_5_REG \
    (CSR_MQM_MSC_BASE + 0x414) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_6_REG \
    (CSR_MQM_MSC_BASE + 0x418) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_7_REG \
    (CSR_MQM_MSC_BASE + 0x41C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_8_REG \
    (CSR_MQM_MSC_BASE + 0x420) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_9_REG \
    (CSR_MQM_MSC_BASE + 0x424) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_10_REG \
    (CSR_MQM_MSC_BASE + 0x428) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_11_REG \
    (CSR_MQM_MSC_BASE + 0x42C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_12_REG \
    (CSR_MQM_MSC_BASE + 0x430) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_13_REG \
    (CSR_MQM_MSC_BASE + 0x434) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_14_REG \
    (CSR_MQM_MSC_BASE + 0x438) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_15_REG \
    (CSR_MQM_MSC_BASE + 0x43C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_16_REG \
    (CSR_MQM_MSC_BASE + 0x440) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_17_REG \
    (CSR_MQM_MSC_BASE + 0x444) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_18_REG \
    (CSR_MQM_MSC_BASE + 0x448) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_19_REG \
    (CSR_MQM_MSC_BASE + 0x44C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_20_REG \
    (CSR_MQM_MSC_BASE + 0x450) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_21_REG \
    (CSR_MQM_MSC_BASE + 0x454) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_22_REG \
    (CSR_MQM_MSC_BASE + 0x458) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_23_REG \
    (CSR_MQM_MSC_BASE + 0x45C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_24_REG \
    (CSR_MQM_MSC_BASE + 0x460) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_25_REG \
    (CSR_MQM_MSC_BASE + 0x464) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_26_REG \
    (CSR_MQM_MSC_BASE + 0x468) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_27_REG \
    (CSR_MQM_MSC_BASE + 0x46C) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_28_REG \
    (CSR_MQM_MSC_BASE + 0x470) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_29_REG \
    (CSR_MQM_MSC_BASE + 0x474) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_30_REG \
    (CSR_MQM_MSC_BASE + 0x478) /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_31_REG \
    (CSR_MQM_MSC_BASE + 0x47C)                                         /* EP Node Weight Configuration Table for NFMQ */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x500) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x504) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x508) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x50C) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x510) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x514) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x518) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x51C) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x520) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x524) /* SOCMSC MQ Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x528)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x52C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x530)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x534)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x538)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x53C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_16_REG (CSR_MQM_MSC_BASE + 0x540)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_17_REG (CSR_MQM_MSC_BASE + 0x544)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_18_REG (CSR_MQM_MSC_BASE + 0x548)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_19_REG (CSR_MQM_MSC_BASE + 0x54C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_20_REG (CSR_MQM_MSC_BASE + 0x550)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_21_REG (CSR_MQM_MSC_BASE + 0x554)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_22_REG (CSR_MQM_MSC_BASE + 0x558)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_23_REG (CSR_MQM_MSC_BASE + 0x55C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_24_REG (CSR_MQM_MSC_BASE + 0x560)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_25_REG (CSR_MQM_MSC_BASE + 0x564)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_26_REG (CSR_MQM_MSC_BASE + 0x568)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_27_REG (CSR_MQM_MSC_BASE + 0x56C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_28_REG (CSR_MQM_MSC_BASE + 0x570)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_29_REG (CSR_MQM_MSC_BASE + 0x574)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_30_REG (CSR_MQM_MSC_BASE + 0x578)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_31_REG (CSR_MQM_MSC_BASE + 0x57C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_32_REG (CSR_MQM_MSC_BASE + 0x580)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_33_REG (CSR_MQM_MSC_BASE + 0x584)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_34_REG (CSR_MQM_MSC_BASE + 0x588)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_35_REG (CSR_MQM_MSC_BASE + 0x58C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_36_REG (CSR_MQM_MSC_BASE + 0x590)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_37_REG (CSR_MQM_MSC_BASE + 0x594)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_38_REG (CSR_MQM_MSC_BASE + 0x598)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_39_REG (CSR_MQM_MSC_BASE + 0x59C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_40_REG (CSR_MQM_MSC_BASE + 0x5A0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_41_REG (CSR_MQM_MSC_BASE + 0x5A4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_42_REG (CSR_MQM_MSC_BASE + 0x5A8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_43_REG (CSR_MQM_MSC_BASE + 0x5AC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_44_REG (CSR_MQM_MSC_BASE + 0x5B0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_45_REG (CSR_MQM_MSC_BASE + 0x5B4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_46_REG (CSR_MQM_MSC_BASE + 0x5B8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_47_REG (CSR_MQM_MSC_BASE + 0x5BC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_48_REG (CSR_MQM_MSC_BASE + 0x5C0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_49_REG (CSR_MQM_MSC_BASE + 0x5C4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_50_REG (CSR_MQM_MSC_BASE + 0x5C8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_51_REG (CSR_MQM_MSC_BASE + 0x5CC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_52_REG (CSR_MQM_MSC_BASE + 0x5D0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_53_REG (CSR_MQM_MSC_BASE + 0x5D4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_54_REG (CSR_MQM_MSC_BASE + 0x5D8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_55_REG (CSR_MQM_MSC_BASE + 0x5DC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_56_REG (CSR_MQM_MSC_BASE + 0x5E0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_57_REG (CSR_MQM_MSC_BASE + 0x5E4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_58_REG (CSR_MQM_MSC_BASE + 0x5E8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_59_REG (CSR_MQM_MSC_BASE + 0x5EC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_60_REG (CSR_MQM_MSC_BASE + 0x5F0)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_61_REG (CSR_MQM_MSC_BASE + 0x5F4)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_62_REG (CSR_MQM_MSC_BASE + 0x5F8)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_63_REG (CSR_MQM_MSC_BASE + 0x5FC)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_64_REG (CSR_MQM_MSC_BASE + 0x600)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_65_REG (CSR_MQM_MSC_BASE + 0x604)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_66_REG (CSR_MQM_MSC_BASE + 0x608)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_67_REG (CSR_MQM_MSC_BASE + 0x60C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_68_REG (CSR_MQM_MSC_BASE + 0x610)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_69_REG (CSR_MQM_MSC_BASE + 0x614)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_70_REG (CSR_MQM_MSC_BASE + 0x618)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_71_REG (CSR_MQM_MSC_BASE + 0x61C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_72_REG (CSR_MQM_MSC_BASE + 0x620)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_73_REG (CSR_MQM_MSC_BASE + 0x624)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_74_REG (CSR_MQM_MSC_BASE + 0x628)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_75_REG (CSR_MQM_MSC_BASE + 0x62C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_76_REG (CSR_MQM_MSC_BASE + 0x630)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_77_REG (CSR_MQM_MSC_BASE + 0x634)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_78_REG (CSR_MQM_MSC_BASE + 0x638)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_79_REG (CSR_MQM_MSC_BASE + 0x63C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_80_REG (CSR_MQM_MSC_BASE + 0x640)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_81_REG (CSR_MQM_MSC_BASE + 0x644)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_82_REG (CSR_MQM_MSC_BASE + 0x648)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_83_REG (CSR_MQM_MSC_BASE + 0x64C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_84_REG (CSR_MQM_MSC_BASE + 0x650)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_85_REG (CSR_MQM_MSC_BASE + 0x654)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_86_REG (CSR_MQM_MSC_BASE + 0x658)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_87_REG (CSR_MQM_MSC_BASE + 0x65C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_88_REG (CSR_MQM_MSC_BASE + 0x660)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_89_REG (CSR_MQM_MSC_BASE + 0x664)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_90_REG (CSR_MQM_MSC_BASE + 0x668)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_91_REG (CSR_MQM_MSC_BASE + 0x66C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_92_REG (CSR_MQM_MSC_BASE + 0x670)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_93_REG (CSR_MQM_MSC_BASE + 0x674)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_94_REG (CSR_MQM_MSC_BASE + 0x678)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_95_REG (CSR_MQM_MSC_BASE + 0x67C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_96_REG (CSR_MQM_MSC_BASE + 0x680)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_97_REG (CSR_MQM_MSC_BASE + 0x684)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_98_REG (CSR_MQM_MSC_BASE + 0x688)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_99_REG (CSR_MQM_MSC_BASE + 0x68C)  /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_100_REG (CSR_MQM_MSC_BASE + 0x690) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_101_REG (CSR_MQM_MSC_BASE + 0x694) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_102_REG (CSR_MQM_MSC_BASE + 0x698) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_103_REG (CSR_MQM_MSC_BASE + 0x69C) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_104_REG (CSR_MQM_MSC_BASE + 0x6A0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_105_REG (CSR_MQM_MSC_BASE + 0x6A4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_106_REG (CSR_MQM_MSC_BASE + 0x6A8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_107_REG (CSR_MQM_MSC_BASE + 0x6AC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_108_REG (CSR_MQM_MSC_BASE + 0x6B0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_109_REG (CSR_MQM_MSC_BASE + 0x6B4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_110_REG (CSR_MQM_MSC_BASE + 0x6B8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_111_REG (CSR_MQM_MSC_BASE + 0x6BC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_112_REG (CSR_MQM_MSC_BASE + 0x6C0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_113_REG (CSR_MQM_MSC_BASE + 0x6C4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_114_REG (CSR_MQM_MSC_BASE + 0x6C8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_115_REG (CSR_MQM_MSC_BASE + 0x6CC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_116_REG (CSR_MQM_MSC_BASE + 0x6D0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_117_REG (CSR_MQM_MSC_BASE + 0x6D4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_118_REG (CSR_MQM_MSC_BASE + 0x6D8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_119_REG (CSR_MQM_MSC_BASE + 0x6DC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_120_REG (CSR_MQM_MSC_BASE + 0x6E0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_121_REG (CSR_MQM_MSC_BASE + 0x6E4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_122_REG (CSR_MQM_MSC_BASE + 0x6E8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_123_REG (CSR_MQM_MSC_BASE + 0x6EC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_124_REG (CSR_MQM_MSC_BASE + 0x6F0) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_125_REG (CSR_MQM_MSC_BASE + 0x6F4) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_126_REG (CSR_MQM_MSC_BASE + 0x6F8) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_127_REG (CSR_MQM_MSC_BASE + 0x6FC) /* SOCMSC MQ Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x700)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x704)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x708)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x70C)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x710)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x714)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x718)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x71C)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x720)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x724)   /* SOCMSC EP Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x728)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x72C)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x730)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x734)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x738)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x73C)  /* SOCMSC EP Node Weight Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_0_REG \
    (CSR_MQM_MSC_BASE + 0x740) /* SOCMSC SERVICE Node Weight Configuration Table */
#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_1_REG \
    (CSR_MQM_MSC_BASE + 0x744) /* SOCMSC SERVICE Node Weight Configuration Table */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_0_REG \
    (CSR_MQM_MSC_BASE + 0x750) /* HOST Node Shaper BPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_1_REG \
    (CSR_MQM_MSC_BASE + 0x754) /* HOST Node Shaper BPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_2_REG \
    (CSR_MQM_MSC_BASE + 0x758) /* HOST Node Shaper BPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_3_REG \
    (CSR_MQM_MSC_BASE + 0x75C) /* HOST Node Shaper BPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_0_REG \
    (CSR_MQM_MSC_BASE + 0x760) /* HOST Node Shaper PPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_1_REG \
    (CSR_MQM_MSC_BASE + 0x764) /* HOST Node Shaper PPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_2_REG \
    (CSR_MQM_MSC_BASE + 0x768) /* HOST Node Shaper PPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_3_REG \
    (CSR_MQM_MSC_BASE + 0x76C) /* HOST Node Shaper PPS Configuration Table for CS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_0_REG \
    (CSR_MQM_MSC_BASE + 0x770) /* HOST Node Shaper BPS_Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_1_REG \
    (CSR_MQM_MSC_BASE + 0x774) /* HOST Node Shaper BPS_Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_2_REG \
    (CSR_MQM_MSC_BASE + 0x778) /* HOST Node Shaper BPS_Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_3_REG \
    (CSR_MQM_MSC_BASE + 0x77C) /* HOST Node Shaper BPS_Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_0_REG \
    (CSR_MQM_MSC_BASE + 0x780) /* HOST Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_1_REG \
    (CSR_MQM_MSC_BASE + 0x784) /* HOST Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_2_REG \
    (CSR_MQM_MSC_BASE + 0x788) /* HOST Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_3_REG \
    (CSR_MQM_MSC_BASE + 0x78C) /* HOST Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_0_REG \
    (CSR_MQM_MSC_BASE + 0x790) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_1_REG \
    (CSR_MQM_MSC_BASE + 0x794) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_2_REG \
    (CSR_MQM_MSC_BASE + 0x798) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_3_REG \
    (CSR_MQM_MSC_BASE + 0x79C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_4_REG \
    (CSR_MQM_MSC_BASE + 0x7A0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_5_REG \
    (CSR_MQM_MSC_BASE + 0x7A4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_6_REG \
    (CSR_MQM_MSC_BASE + 0x7A8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_7_REG \
    (CSR_MQM_MSC_BASE + 0x7AC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_8_REG \
    (CSR_MQM_MSC_BASE + 0x7B0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_9_REG \
    (CSR_MQM_MSC_BASE + 0x7B4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_10_REG \
    (CSR_MQM_MSC_BASE + 0x7B8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_11_REG \
    (CSR_MQM_MSC_BASE + 0x7BC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_12_REG \
    (CSR_MQM_MSC_BASE + 0x7C0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_13_REG \
    (CSR_MQM_MSC_BASE + 0x7C4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_14_REG \
    (CSR_MQM_MSC_BASE + 0x7C8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_15_REG \
    (CSR_MQM_MSC_BASE + 0x7CC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_16_REG \
    (CSR_MQM_MSC_BASE + 0x7D0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_17_REG \
    (CSR_MQM_MSC_BASE + 0x7D4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_18_REG \
    (CSR_MQM_MSC_BASE + 0x7D8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_19_REG \
    (CSR_MQM_MSC_BASE + 0x7DC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_20_REG \
    (CSR_MQM_MSC_BASE + 0x7E0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_21_REG \
    (CSR_MQM_MSC_BASE + 0x7E4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_22_REG \
    (CSR_MQM_MSC_BASE + 0x7E8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_23_REG \
    (CSR_MQM_MSC_BASE + 0x7EC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_24_REG \
    (CSR_MQM_MSC_BASE + 0x7F0) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_25_REG \
    (CSR_MQM_MSC_BASE + 0x7F4) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_26_REG \
    (CSR_MQM_MSC_BASE + 0x7F8) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_27_REG \
    (CSR_MQM_MSC_BASE + 0x7FC) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_28_REG \
    (CSR_MQM_MSC_BASE + 0x800) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_29_REG \
    (CSR_MQM_MSC_BASE + 0x804) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_30_REG \
    (CSR_MQM_MSC_BASE + 0x808) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_31_REG \
    (CSR_MQM_MSC_BASE + 0x80C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_0_REG \
    (CSR_MQM_MSC_BASE + 0x810) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_1_REG \
    (CSR_MQM_MSC_BASE + 0x814) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_2_REG \
    (CSR_MQM_MSC_BASE + 0x818) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_3_REG \
    (CSR_MQM_MSC_BASE + 0x81C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_4_REG \
    (CSR_MQM_MSC_BASE + 0x820) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_5_REG \
    (CSR_MQM_MSC_BASE + 0x824) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_6_REG \
    (CSR_MQM_MSC_BASE + 0x828) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_7_REG \
    (CSR_MQM_MSC_BASE + 0x82C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_8_REG \
    (CSR_MQM_MSC_BASE + 0x830) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_9_REG \
    (CSR_MQM_MSC_BASE + 0x834) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_10_REG \
    (CSR_MQM_MSC_BASE + 0x838) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_11_REG \
    (CSR_MQM_MSC_BASE + 0x83C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_12_REG \
    (CSR_MQM_MSC_BASE + 0x840) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_13_REG \
    (CSR_MQM_MSC_BASE + 0x844) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_14_REG \
    (CSR_MQM_MSC_BASE + 0x848) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_15_REG \
    (CSR_MQM_MSC_BASE + 0x84C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_16_REG \
    (CSR_MQM_MSC_BASE + 0x850) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_17_REG \
    (CSR_MQM_MSC_BASE + 0x854) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_18_REG \
    (CSR_MQM_MSC_BASE + 0x858) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_19_REG \
    (CSR_MQM_MSC_BASE + 0x85C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_20_REG \
    (CSR_MQM_MSC_BASE + 0x860) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_21_REG \
    (CSR_MQM_MSC_BASE + 0x864) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_22_REG \
    (CSR_MQM_MSC_BASE + 0x868) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_23_REG \
    (CSR_MQM_MSC_BASE + 0x86C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_24_REG \
    (CSR_MQM_MSC_BASE + 0x870) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_25_REG \
    (CSR_MQM_MSC_BASE + 0x874) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_26_REG \
    (CSR_MQM_MSC_BASE + 0x878) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_27_REG \
    (CSR_MQM_MSC_BASE + 0x87C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_28_REG \
    (CSR_MQM_MSC_BASE + 0x880) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_29_REG \
    (CSR_MQM_MSC_BASE + 0x884) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_30_REG \
    (CSR_MQM_MSC_BASE + 0x888) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_31_REG \
    (CSR_MQM_MSC_BASE + 0x88C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_0_REG \
    (CSR_MQM_MSC_BASE + 0x890) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_1_REG \
    (CSR_MQM_MSC_BASE + 0x894) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_2_REG \
    (CSR_MQM_MSC_BASE + 0x898) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_3_REG \
    (CSR_MQM_MSC_BASE + 0x89C) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_4_REG \
    (CSR_MQM_MSC_BASE + 0x8A0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_5_REG \
    (CSR_MQM_MSC_BASE + 0x8A4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_6_REG \
    (CSR_MQM_MSC_BASE + 0x8A8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_7_REG \
    (CSR_MQM_MSC_BASE + 0x8AC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_8_REG \
    (CSR_MQM_MSC_BASE + 0x8B0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_9_REG \
    (CSR_MQM_MSC_BASE + 0x8B4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_10_REG \
    (CSR_MQM_MSC_BASE + 0x8B8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_11_REG \
    (CSR_MQM_MSC_BASE + 0x8BC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_12_REG \
    (CSR_MQM_MSC_BASE + 0x8C0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_13_REG \
    (CSR_MQM_MSC_BASE + 0x8C4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_14_REG \
    (CSR_MQM_MSC_BASE + 0x8C8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_15_REG \
    (CSR_MQM_MSC_BASE + 0x8CC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_16_REG \
    (CSR_MQM_MSC_BASE + 0x8D0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_17_REG \
    (CSR_MQM_MSC_BASE + 0x8D4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_18_REG \
    (CSR_MQM_MSC_BASE + 0x8D8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_19_REG \
    (CSR_MQM_MSC_BASE + 0x8DC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_20_REG \
    (CSR_MQM_MSC_BASE + 0x8E0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_21_REG \
    (CSR_MQM_MSC_BASE + 0x8E4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_22_REG \
    (CSR_MQM_MSC_BASE + 0x8E8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_23_REG \
    (CSR_MQM_MSC_BASE + 0x8EC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_24_REG \
    (CSR_MQM_MSC_BASE + 0x8F0) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_25_REG \
    (CSR_MQM_MSC_BASE + 0x8F4) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_26_REG \
    (CSR_MQM_MSC_BASE + 0x8F8) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_27_REG \
    (CSR_MQM_MSC_BASE + 0x8FC) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_28_REG \
    (CSR_MQM_MSC_BASE + 0x900) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_29_REG \
    (CSR_MQM_MSC_BASE + 0x904) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_30_REG \
    (CSR_MQM_MSC_BASE + 0x908) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_31_REG \
    (CSR_MQM_MSC_BASE + 0x90C) /* EP Node Shaper BPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_0_REG \
    (CSR_MQM_MSC_BASE + 0x910) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_1_REG \
    (CSR_MQM_MSC_BASE + 0x914) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_2_REG \
    (CSR_MQM_MSC_BASE + 0x918) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_3_REG \
    (CSR_MQM_MSC_BASE + 0x91C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_4_REG \
    (CSR_MQM_MSC_BASE + 0x920) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_5_REG \
    (CSR_MQM_MSC_BASE + 0x924) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_6_REG \
    (CSR_MQM_MSC_BASE + 0x928) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_7_REG \
    (CSR_MQM_MSC_BASE + 0x92C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_8_REG \
    (CSR_MQM_MSC_BASE + 0x930) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_9_REG \
    (CSR_MQM_MSC_BASE + 0x934) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_10_REG \
    (CSR_MQM_MSC_BASE + 0x938) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_11_REG \
    (CSR_MQM_MSC_BASE + 0x93C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_12_REG \
    (CSR_MQM_MSC_BASE + 0x940) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_13_REG \
    (CSR_MQM_MSC_BASE + 0x944) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_14_REG \
    (CSR_MQM_MSC_BASE + 0x948) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_15_REG \
    (CSR_MQM_MSC_BASE + 0x94C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_16_REG \
    (CSR_MQM_MSC_BASE + 0x950) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_17_REG \
    (CSR_MQM_MSC_BASE + 0x954) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_18_REG \
    (CSR_MQM_MSC_BASE + 0x958) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_19_REG \
    (CSR_MQM_MSC_BASE + 0x95C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_20_REG \
    (CSR_MQM_MSC_BASE + 0x960) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_21_REG \
    (CSR_MQM_MSC_BASE + 0x964) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_22_REG \
    (CSR_MQM_MSC_BASE + 0x968) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_23_REG \
    (CSR_MQM_MSC_BASE + 0x96C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_24_REG \
    (CSR_MQM_MSC_BASE + 0x970) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_25_REG \
    (CSR_MQM_MSC_BASE + 0x974) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_26_REG \
    (CSR_MQM_MSC_BASE + 0x978) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_27_REG \
    (CSR_MQM_MSC_BASE + 0x97C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_28_REG \
    (CSR_MQM_MSC_BASE + 0x980) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_29_REG \
    (CSR_MQM_MSC_BASE + 0x984) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_30_REG \
    (CSR_MQM_MSC_BASE + 0x988) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_31_REG \
    (CSR_MQM_MSC_BASE + 0x98C) /* EP Node Shaper PPS Configuration Table for CMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_0_REG \
    (CSR_MQM_MSC_BASE + 0x990) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_1_REG \
    (CSR_MQM_MSC_BASE + 0x994) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_2_REG \
    (CSR_MQM_MSC_BASE + 0x998) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_3_REG \
    (CSR_MQM_MSC_BASE + 0x99C) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_4_REG \
    (CSR_MQM_MSC_BASE + 0x9A0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_5_REG \
    (CSR_MQM_MSC_BASE + 0x9A4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_6_REG \
    (CSR_MQM_MSC_BASE + 0x9A8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_7_REG \
    (CSR_MQM_MSC_BASE + 0x9AC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_8_REG \
    (CSR_MQM_MSC_BASE + 0x9B0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_9_REG \
    (CSR_MQM_MSC_BASE + 0x9B4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_10_REG \
    (CSR_MQM_MSC_BASE + 0x9B8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_11_REG \
    (CSR_MQM_MSC_BASE + 0x9BC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_12_REG \
    (CSR_MQM_MSC_BASE + 0x9C0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_13_REG \
    (CSR_MQM_MSC_BASE + 0x9C4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_14_REG \
    (CSR_MQM_MSC_BASE + 0x9C8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_15_REG \
    (CSR_MQM_MSC_BASE + 0x9CC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_16_REG \
    (CSR_MQM_MSC_BASE + 0x9D0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_17_REG \
    (CSR_MQM_MSC_BASE + 0x9D4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_18_REG \
    (CSR_MQM_MSC_BASE + 0x9D8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_19_REG \
    (CSR_MQM_MSC_BASE + 0x9DC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_20_REG \
    (CSR_MQM_MSC_BASE + 0x9E0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_21_REG \
    (CSR_MQM_MSC_BASE + 0x9E4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_22_REG \
    (CSR_MQM_MSC_BASE + 0x9E8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_23_REG \
    (CSR_MQM_MSC_BASE + 0x9EC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_24_REG \
    (CSR_MQM_MSC_BASE + 0x9F0) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_25_REG \
    (CSR_MQM_MSC_BASE + 0x9F4) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_26_REG \
    (CSR_MQM_MSC_BASE + 0x9F8) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_27_REG \
    (CSR_MQM_MSC_BASE + 0x9FC) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_28_REG \
    (CSR_MQM_MSC_BASE + 0xA00) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_29_REG \
    (CSR_MQM_MSC_BASE + 0xA04) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_30_REG \
    (CSR_MQM_MSC_BASE + 0xA08) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_31_REG \
    (CSR_MQM_MSC_BASE + 0xA0C) /* EP Node Shaper BPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_0_REG \
    (CSR_MQM_MSC_BASE + 0xA10) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_1_REG \
    (CSR_MQM_MSC_BASE + 0xA14) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_2_REG \
    (CSR_MQM_MSC_BASE + 0xA18) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_3_REG \
    (CSR_MQM_MSC_BASE + 0xA1C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_4_REG \
    (CSR_MQM_MSC_BASE + 0xA20) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_5_REG \
    (CSR_MQM_MSC_BASE + 0xA24) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_6_REG \
    (CSR_MQM_MSC_BASE + 0xA28) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_7_REG \
    (CSR_MQM_MSC_BASE + 0xA2C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_8_REG \
    (CSR_MQM_MSC_BASE + 0xA30) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_9_REG \
    (CSR_MQM_MSC_BASE + 0xA34) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_10_REG \
    (CSR_MQM_MSC_BASE + 0xA38) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_11_REG \
    (CSR_MQM_MSC_BASE + 0xA3C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_12_REG \
    (CSR_MQM_MSC_BASE + 0xA40) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_13_REG \
    (CSR_MQM_MSC_BASE + 0xA44) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_14_REG \
    (CSR_MQM_MSC_BASE + 0xA48) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_15_REG \
    (CSR_MQM_MSC_BASE + 0xA4C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_16_REG \
    (CSR_MQM_MSC_BASE + 0xA50) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_17_REG \
    (CSR_MQM_MSC_BASE + 0xA54) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_18_REG \
    (CSR_MQM_MSC_BASE + 0xA58) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_19_REG \
    (CSR_MQM_MSC_BASE + 0xA5C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_20_REG \
    (CSR_MQM_MSC_BASE + 0xA60) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_21_REG \
    (CSR_MQM_MSC_BASE + 0xA64) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_22_REG \
    (CSR_MQM_MSC_BASE + 0xA68) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_23_REG \
    (CSR_MQM_MSC_BASE + 0xA6C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_24_REG \
    (CSR_MQM_MSC_BASE + 0xA70) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_25_REG \
    (CSR_MQM_MSC_BASE + 0xA74) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_26_REG \
    (CSR_MQM_MSC_BASE + 0xA78) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_27_REG \
    (CSR_MQM_MSC_BASE + 0xA7C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_28_REG \
    (CSR_MQM_MSC_BASE + 0xA80) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_29_REG \
    (CSR_MQM_MSC_BASE + 0xA84) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_30_REG \
    (CSR_MQM_MSC_BASE + 0xA88) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_31_REG \
    (CSR_MQM_MSC_BASE + 0xA8C) /* EP Node Shaper PPS Configuration Table for NFMQ */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xB00)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xB04)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xB08)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xB0C)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xB10)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xB14)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xB18)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xB1C)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xB20)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xB24)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xB28) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xB2C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xB30) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xB34) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xB38) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xB3C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xB40) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xB44) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xB48) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xB4C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xB50) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xB54) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xB58) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xB5C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xB60) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xB64) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xB68) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xB6C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xB70) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xB74) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xB78) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xB7C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xB80) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xB84) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xB88) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xB8C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xB90) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xB94) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xB98) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xB9C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xBA0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xBA4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xBA8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xBAC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xBB0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xBB4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xBB8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xBBC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xBC0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xBC4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xBC8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xBCC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xBD0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xBD4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xBD8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xBDC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xBE0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xBE4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xBE8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xBEC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xBF0) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xBF4) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xBF8) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xBFC) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xC00) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xC04) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xC08) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xC0C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xC10) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xC14) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xC18) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xC1C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xC20) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xC24) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xC28) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xC2C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xC30) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xC34) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xC38) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xC3C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xC40) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xC44) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xC48) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xC4C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xC50) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xC54) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xC58) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xC5C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xC60) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xC64) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xC68) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xC6C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xC70) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xC74) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xC78) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xC7C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xC80) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xC84) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xC88) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xC8C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_100_REG \
    (CSR_MQM_MSC_BASE + 0xC90) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_101_REG \
    (CSR_MQM_MSC_BASE + 0xC94) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_102_REG \
    (CSR_MQM_MSC_BASE + 0xC98) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_103_REG \
    (CSR_MQM_MSC_BASE + 0xC9C) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_104_REG \
    (CSR_MQM_MSC_BASE + 0xCA0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_105_REG \
    (CSR_MQM_MSC_BASE + 0xCA4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_106_REG \
    (CSR_MQM_MSC_BASE + 0xCA8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_107_REG \
    (CSR_MQM_MSC_BASE + 0xCAC) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_108_REG \
    (CSR_MQM_MSC_BASE + 0xCB0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_109_REG \
    (CSR_MQM_MSC_BASE + 0xCB4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_110_REG \
    (CSR_MQM_MSC_BASE + 0xCB8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_111_REG \
    (CSR_MQM_MSC_BASE + 0xCBC) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_112_REG \
    (CSR_MQM_MSC_BASE + 0xCC0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_113_REG \
    (CSR_MQM_MSC_BASE + 0xCC4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_114_REG \
    (CSR_MQM_MSC_BASE + 0xCC8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_115_REG \
    (CSR_MQM_MSC_BASE + 0xCCC) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_116_REG \
    (CSR_MQM_MSC_BASE + 0xCD0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_117_REG \
    (CSR_MQM_MSC_BASE + 0xCD4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_118_REG \
    (CSR_MQM_MSC_BASE + 0xCD8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_119_REG \
    (CSR_MQM_MSC_BASE + 0xCDC) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_120_REG \
    (CSR_MQM_MSC_BASE + 0xCE0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_121_REG \
    (CSR_MQM_MSC_BASE + 0xCE4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_122_REG \
    (CSR_MQM_MSC_BASE + 0xCE8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_123_REG \
    (CSR_MQM_MSC_BASE + 0xCEC) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_124_REG \
    (CSR_MQM_MSC_BASE + 0xCF0) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_125_REG \
    (CSR_MQM_MSC_BASE + 0xCF4) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_126_REG \
    (CSR_MQM_MSC_BASE + 0xCF8) /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_127_REG \
    (CSR_MQM_MSC_BASE + 0xCFC)                                           /* SOCMQ Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xD00)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xD04)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xD08)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xD0C)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xD10)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xD14)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xD18)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xD1C)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xD20)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xD24)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xD28) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xD2C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xD30) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xD34) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xD38) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xD3C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xD40) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xD44) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xD48) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xD4C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xD50) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xD54) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xD58) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xD5C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xD60) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xD64) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xD68) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xD6C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xD70) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xD74) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xD78) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xD7C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xD80) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xD84) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xD88) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xD8C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xD90) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xD94) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xD98) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xD9C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xDA0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xDA4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xDA8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xDAC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xDB0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xDB4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xDB8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xDBC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xDC0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xDC4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xDC8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xDCC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xDD0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xDD4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xDD8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xDDC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xDE0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xDE4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xDE8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xDEC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xDF0) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xDF4) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xDF8) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xDFC) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xE00) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xE04) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xE08) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xE0C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xE10) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xE14) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xE18) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xE1C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xE20) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xE24) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xE28) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xE2C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xE30) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xE34) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xE38) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xE3C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xE40) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xE44) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xE48) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xE4C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xE50) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xE54) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xE58) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xE5C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xE60) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xE64) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xE68) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xE6C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xE70) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xE74) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xE78) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xE7C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xE80) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xE84) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xE88) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xE8C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_100_REG \
    (CSR_MQM_MSC_BASE + 0xE90) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_101_REG \
    (CSR_MQM_MSC_BASE + 0xE94) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_102_REG \
    (CSR_MQM_MSC_BASE + 0xE98) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_103_REG \
    (CSR_MQM_MSC_BASE + 0xE9C) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_104_REG \
    (CSR_MQM_MSC_BASE + 0xEA0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_105_REG \
    (CSR_MQM_MSC_BASE + 0xEA4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_106_REG \
    (CSR_MQM_MSC_BASE + 0xEA8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_107_REG \
    (CSR_MQM_MSC_BASE + 0xEAC) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_108_REG \
    (CSR_MQM_MSC_BASE + 0xEB0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_109_REG \
    (CSR_MQM_MSC_BASE + 0xEB4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_110_REG \
    (CSR_MQM_MSC_BASE + 0xEB8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_111_REG \
    (CSR_MQM_MSC_BASE + 0xEBC) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_112_REG \
    (CSR_MQM_MSC_BASE + 0xEC0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_113_REG \
    (CSR_MQM_MSC_BASE + 0xEC4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_114_REG \
    (CSR_MQM_MSC_BASE + 0xEC8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_115_REG \
    (CSR_MQM_MSC_BASE + 0xECC) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_116_REG \
    (CSR_MQM_MSC_BASE + 0xED0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_117_REG \
    (CSR_MQM_MSC_BASE + 0xED4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_118_REG \
    (CSR_MQM_MSC_BASE + 0xED8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_119_REG \
    (CSR_MQM_MSC_BASE + 0xEDC) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_120_REG \
    (CSR_MQM_MSC_BASE + 0xEE0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_121_REG \
    (CSR_MQM_MSC_BASE + 0xEE4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_122_REG \
    (CSR_MQM_MSC_BASE + 0xEE8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_123_REG \
    (CSR_MQM_MSC_BASE + 0xEEC) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_124_REG \
    (CSR_MQM_MSC_BASE + 0xEF0) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_125_REG \
    (CSR_MQM_MSC_BASE + 0xEF4) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_126_REG \
    (CSR_MQM_MSC_BASE + 0xEF8) /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_127_REG \
    (CSR_MQM_MSC_BASE + 0xEFC)                                           /* SOCMQ Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF00)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF04)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF08)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF0C)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF10)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF14)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF18)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF1C)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF20)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF24)  /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF28) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF2C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF30) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF34) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF38) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF3C) /* SOCMQ Node Shaper BPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF40)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF44)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF48)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF4C)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF50)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF54)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF58)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF5C)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF60)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF64)  /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF68) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF6C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF70) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF74) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF78) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF7C) /* SOCMQ Node Shaper PPS Configuration Table \
                                                                          */
#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_0_REG \
    (CSR_MQM_MSC_BASE + 0xF80) /* SOC Service Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_1_REG \
    (CSR_MQM_MSC_BASE + 0xF84) /* SOC Service Node Shaper BPS Configuration Table */
#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_0_REG \
    (CSR_MQM_MSC_BASE + 0xF88) /* SOC Service Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_1_REG \
    (CSR_MQM_MSC_BASE + 0xF8C) /* SOC Service Node Shaper PPS Configuration Table */
#define CSR_MQM_MSC_SOCRT_SHAP_BPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF90) /* SOC Root Node Shaper BPS Configuration Table \
                                                                       */
#define CSR_MQM_MSC_SOCRT_SHAP_PPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF94) /* SOC Root Node Shaper PPS Configuration Table \
                                                                       */
#define CSR_MQM_MSC_MSC_SHAP_BYPASS_CFG_REG (CSR_MQM_MSC_BASE + 0x1200) /* MSC Shaper Bypass Configuration */
#define CSR_MQM_MSC_MSC_HOST_ROOT_XON_CFG_REG \
    (CSR_MQM_MSC_BASE + 0x1204) /* The XON Configuration of the HOST ROOT node */
#define CSR_MQM_MSC_MSC_SOC_ROOT_XON_CFG_REG \
    (CSR_MQM_MSC_BASE + 0x1208) /* The XON Configuration of the SOC ROOT node */
#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NS_REG \
    (CSR_MQM_MSC_BASE + 0x120C) /* The XON Configuration of the NS HOST EP node */
#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NFMQ_REG \
    (CSR_MQM_MSC_BASE + 0x1210) /* The XON Configuration of the NFMQ HOST EP node */
#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_CMQ_REG \
    (CSR_MQM_MSC_BASE + 0x1214) /* The XON Configuration of the CMQ HOST EP node */
#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_0_REG \
    (CSR_MQM_MSC_BASE + 0x1220) /* The XON Configuration of the SOCMSC NS MQ node */
#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_1_REG \
    (CSR_MQM_MSC_BASE + 0x1224) /* The XON Configuration of the SOCMSC NS MQ node */
#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_2_REG \
    (CSR_MQM_MSC_BASE + 0x1228) /* The XON Configuration of the SOCMSC NS MQ node */
#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_3_REG \
    (CSR_MQM_MSC_BASE + 0x122C) /* The XON Configuration of the SOCMSC NS MQ node */
#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA0_REG \
    (CSR_MQM_MSC_BASE + 0x1230) /* MSC Port backpress status Register 0 from PRM */
#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA1_REG \
    (CSR_MQM_MSC_BASE + 0x1234) /* MSC Port backpress status Register 1 from PRM */
#define CSR_MQM_MSC_MSC_QU_COS_BP_STA0_REG \
    (CSR_MQM_MSC_BASE + 0x1238) /* MSC COS Level backpress status Register for NMQ EP0~EP3 */
#define CSR_MQM_MSC_MSC_QU_COS_BP_STA1_REG \
    (CSR_MQM_MSC_BASE + 0x123C) /* MSC COS Level backpress status Register for NMQ EP4~EP7 */
#define CSR_MQM_MSC_SOCMSC_RT_EP_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1240) /* SOC MSC backpress status Register */
#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA0_REG \
    (CSR_MQM_MSC_BASE + 0x1244) /* SOCMSC QUEUE Level backpress status Register 0 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA1_REG \
    (CSR_MQM_MSC_BASE + 0x1248) /* SOCMSC QUEUE Level backpress status Register 1 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA2_REG \
    (CSR_MQM_MSC_BASE + 0x124C) /* SOCMSC QUEUE Level backpress status Register 2 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA3_REG \
    (CSR_MQM_MSC_BASE + 0x1250) /* SOCMSC QUEUE Level backpress status Register 3 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA0_REG \
    (CSR_MQM_MSC_BASE + 0x1254) /* SOCMSC QUEUE Level eligible status Register 0 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA1_REG \
    (CSR_MQM_MSC_BASE + 0x1258) /* SOCMSC QUEUE Level eligible status Register 1 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA2_REG \
    (CSR_MQM_MSC_BASE + 0x125C) /* SOCMSC QUEUE Level eligible status Register 2 */
#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA3_REG \
    (CSR_MQM_MSC_BASE + 0x1260) /* SOCMSC QUEUE Level eligible status Register 3 */
#define CSR_MQM_MSC_MSC_RT_HOST_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1264) /* MSC root host backpress status Register */
#define CSR_MQM_MSC_MSC_HOSTEP_NS_BP_STA_REG \
    (CSR_MQM_MSC_BASE + 0x1268) /* MSC NS HSOT_EP Level backpress status Register */
#define CSR_MQM_MSC_MSC_HOSTEP_NFMQ_BP_STA_REG \
    (CSR_MQM_MSC_BASE + 0x126C) /* MSC NFMQ HSOT_EP Level backpress status Register */
#define CSR_MQM_MSC_MSC_HOSTEP_CMQ_BP_STA_REG \
    (CSR_MQM_MSC_BASE + 0x1270) /* MSC CMQ HSOT_EP Level backpress status Register */
#define CSR_MQM_MSC_MSC_FIFO_TH_CFG_REG (CSR_MQM_MSC_BASE + 0x1274)         /* The Threshold Config Of MSC FIFO */
#define CSR_MQM_MSC_MSC_FIFO_ST0_REG (CSR_MQM_MSC_BASE + 0x1290)            /* fifo full and empt state */
#define CSR_MQM_MSC_MSC_FIFO_ST1_REG (CSR_MQM_MSC_BASE + 0x1294)            /* fifo full and empt state */
#define CSR_MQM_MSC_MSC_FIFO_ST2_REG (CSR_MQM_MSC_BASE + 0x1298)            /* fifo full and empt state */
#define CSR_MQM_MSC_MSC_FIFO_ST3_REG (CSR_MQM_MSC_BASE + 0x129C)            /* fifo full and empt state */
#define CSR_MQM_MSC_CMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A0)           /* Command MQ ENQ UP count */
#define CSR_MQM_MSC_NFMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A4)          /* Non-filter MQ ENQ UP count */
#define CSR_MQM_MSC_NMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A8)           /* Normal MQ ENQ UP count */
#define CSR_MQM_MSC_CMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12AC)             /* Command MQ schedule count */
#define CSR_MQM_MSC_NFMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B0)            /* Non-filter MQ schedule count. */
#define CSR_MQM_MSC_NMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B4)             /* Normal MQ schedule cnt numbers */
#define CSR_MQM_MSC_SOCCMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12B8)           /* SOC Command MQ UP count */
#define CSR_MQM_MSC_SOCNMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12BC)           /* SOC NMQ UP count. */
#define CSR_MQM_MSC_SOCCMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C0)          /* SOC Command MQ schedule count */
#define CSR_MQM_MSC_SOCNMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C4)          /* SOC NMQ schedule count. */
#define CSR_MQM_MSC_CMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C8)        /* Command MQ EMPT schedule count */
#define CSR_MQM_MSC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12CC)       /* Non-filter MQ EMPT schedule count */
#define CSR_MQM_MSC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12D0)        /* Normal MQ EMPT schedule count */
#define CSR_MQM_MSC_CMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D4)           /* Command MQ DU count */
#define CSR_MQM_MSC_NFMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D8)          /* Non-filter MQ DU count */
#define CSR_MQM_MSC_NMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12DC)           /* Normal MQ DU count */
#define CSR_MQM_MSC_SOCCMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E0)           /* SOC Command MQ DU count */
#define CSR_MQM_MSC_SOCNMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E4)           /* SOC NMQ DU count. */
#define CSR_MQM_MSC_MSC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12E8)    /* MSC MEMORY ECC 1BIT ERR count */
#define CSR_MQM_MSC_MSC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12EC)    /* MSC MEMORY ECC 2BIT ERR count */
#define CSR_MQM_MSC_SCH_MQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1320)          /* MQ DFX NUM configure */
#define CSR_MQM_MSC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1324)       /* MQ DFX NUM  ENQ UP count */
#define CSR_MQM_MSC_SCH_MQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x1328)      /* MQ DFX NUM  DEQ SCH count */
#define CSR_MQM_MSC_SCH_MQ_DFX_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x132C) /* MQ DFX NUM  DEQ EMPT SCH count */
#define CSR_MQM_MSC_SCH_MQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1330)       /* MQ DFX NUM  DU count */
#define CSR_MQM_MSC_SCH_SOCMQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1334)       /* SOCMQ DFX NUM configure */
#define CSR_MQM_MSC_SCH_SOCMQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1338)    /* SOCMQ DFX NUM  ENQ UP count */
#define CSR_MQM_MSC_SCH_SOCMQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x133C)   /* SOCMQ DFX NUM  DEQ SCH count */
#define CSR_MQM_MSC_SCH_SOCMQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1340)    /* SOCMQ DFX NUM  DU count */
#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR0_REG \
    (CSR_MQM_MSC_BASE + 0x1344) /* MQM SOCMSC MCD DU INFO 0  status Register */
#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR1_REG \
    (CSR_MQM_MSC_BASE + 0x1348) /* MQM SOCMSC MCD DU INFO 1  status Register */
#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR0_REG \
    (CSR_MQM_MSC_BASE + 0x134C) /* MQM MSC CS MCD DU INFO 0  status Register */
#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR1_REG \
    (CSR_MQM_MSC_BASE + 0x1350) /* MQM MSC CS MCD DU INFO 1  status Register */
#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR2_REG \
    (CSR_MQM_MSC_BASE + 0x1354) /* MQM MSC CS MCD DU INFO 2  status Register */
#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR0_REG \
    (CSR_MQM_MSC_BASE + 0x1358) /* MQM MSC NS MCD DU INFO 0  status Register */
#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR1_REG \
    (CSR_MQM_MSC_BASE + 0x135C) /* MQM MSC NS MCD DU INFO 1  status Register */
#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR2_REG \
    (CSR_MQM_MSC_BASE + 0x1360) /* MQM MSC NS MCD DU INFO 2  status Register */

/* MQM_DEQC Base address of Module's Register */
#define CSR_MQM_DEQC_BASE (0xE000)

/* **************************************************************************** */
/*                      MQM_DEQC Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MQM_DEQC_DEQC_RW_RSV0_REG (CSR_MQM_DEQC_BASE + 0x0)            /* DEQC Read-Write  Register0 for Reserve. */
#define CSR_MQM_DEQC_DEQC_RW_RSV1_REG (CSR_MQM_DEQC_BASE + 0x4)            /* DEQC Read-Write  Register1 for Reserve. */
#define CSR_MQM_DEQC_DEQC_RW_RSV2_REG (CSR_MQM_DEQC_BASE + 0x8)            /* DEQC Read-Write  Register2 for Reserve. */
#define CSR_MQM_DEQC_DEQC_RW_RSV3_REG (CSR_MQM_DEQC_BASE + 0xC)            /* DEQC Read-Write  Register3 for Reserve. */
#define CSR_MQM_DEQC_DEQC_INDRECT_CTRL_REG (CSR_MQM_DEQC_BASE + 0x10)      /* DEQC Indirect access ctrl Register。 */
#define CSR_MQM_DEQC_DEQC_INDRECT_TIMEOUT_REG (CSR_MQM_DEQC_BASE + 0x14)   /* DEQC Indirect Access Timeout Register。 */
#define CSR_MQM_DEQC_DEQC_INDRECT_DATA_REG (CSR_MQM_DEQC_BASE + 0x18)      /* DEQC Indirect Access Data Register. */
#define CSR_MQM_DEQC_DEQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_DEQC_BASE + 0x20) /* RAM ECC BYPASS控制寄存器 */
#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_DEQC_BASE + 0x24) /* RAM CTRL_BUS寄存器0 */
#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_DEQC_BASE + 0x28) /* RAM CTRL_BUS寄存器1 */
#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_DEQC_BASE + 0x2C) /* RAM CTRL_BUS寄存器2 */
#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_DEQC_BASE + 0x30) /* RAM CTRL_BUS寄存器3 */
#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_DEQC_BASE + 0x34) /* RAM CTRL_BUS寄存器4 */
#define CSR_MQM_DEQC_DEQC_INT_VECTOR_REG (CSR_MQM_DEQC_BASE + 0x100)   /* DEQC Internal ERR Interrupt Vector Register. \
                                                                        */
#define CSR_MQM_DEQC_DEQC_INT_REG (CSR_MQM_DEQC_BASE + 0x104)          /* DEQC Internal ERR Interrupt Register. */
#define CSR_MQM_DEQC_DEQC_INT_EN_REG (CSR_MQM_DEQC_BASE + 0x108)       /* DEQC Internal ERR Interrupt Mask Register. */
#define CSR_MQM_DEQC_DEQC_MEM_1BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x10C) /* DEQC 1Bit ECC Check Err Register. */
#define CSR_MQM_DEQC_DEQC_MEM_2BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x110) /* DEQC 2Bit ECC Check Err Register. */
#define CSR_MQM_DEQC_DEQC_ENMQ_BIND_CONFIG_ERR_REG (CSR_MQM_DEQC_BASE + 0x114) /* DEQC ENMQ BIND CONFIG Err Register. \
                                                                                */
#define CSR_MQM_DEQC_DEQC_ENFMQ_BIND_CONFIG_ERR_REG \
    (CSR_MQM_DEQC_BASE + 0x118)                                       /* DEQC ENFMQ BIND CONFIG Err Register. */
#define CSR_MQM_DEQC_DEQC_MEM_ERR_REQ_REG (CSR_MQM_DEQC_BASE + 0x150) /* DEQC Internal Memory ERR Req Register. */
#define CSR_MQM_DEQC_DEQC_FIFO_INT_REG (CSR_MQM_DEQC_BASE + 0x154)    /* DEQC FIFO Write Interrupt Register. */
#define CSR_MQM_DEQC_DEQC_FIFO_WR_INT_MASK_REG \
    (CSR_MQM_DEQC_BASE + 0x158)                                           /* DEQC FIFO Write Interrupt Mask Register. */
#define CSR_MQM_DEQC_DEQC_TIMES_COUNT_CFG_REG (CSR_MQM_DEQC_BASE + 0x200) /* DEQC TIMES Count Configuration Register \
                                                                           */
#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN0_REG (CSR_MQM_DEQC_BASE + 0x204)   /* DEQC Queue Descriptors Block Size. */
#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN1_REG (CSR_MQM_DEQC_BASE + 0x208)   /* DEQC Queue Descriptors Block Size. */
#define CSR_MQM_DEQC_DEQC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_DEQC_BASE + 0x20C) /* DEQC ROOT CRR WEIGHT Config */
#define CSR_MQM_DEQC_DEQC_WEIGHT_OFFSET_REG (CSR_MQM_DEQC_BASE + 0x210)       /* DEQC Weight Offset Register. */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_0_REG \
    (CSR_MQM_DEQC_BASE + 0x300) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_1_REG \
    (CSR_MQM_DEQC_BASE + 0x304) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_2_REG \
    (CSR_MQM_DEQC_BASE + 0x308) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_3_REG \
    (CSR_MQM_DEQC_BASE + 0x30C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_4_REG \
    (CSR_MQM_DEQC_BASE + 0x310) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_5_REG \
    (CSR_MQM_DEQC_BASE + 0x314) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_6_REG \
    (CSR_MQM_DEQC_BASE + 0x318) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_7_REG \
    (CSR_MQM_DEQC_BASE + 0x31C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_8_REG \
    (CSR_MQM_DEQC_BASE + 0x320) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_9_REG \
    (CSR_MQM_DEQC_BASE + 0x324) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_10_REG \
    (CSR_MQM_DEQC_BASE + 0x328) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_11_REG \
    (CSR_MQM_DEQC_BASE + 0x32C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_12_REG \
    (CSR_MQM_DEQC_BASE + 0x330) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_13_REG \
    (CSR_MQM_DEQC_BASE + 0x334) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_14_REG \
    (CSR_MQM_DEQC_BASE + 0x338) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_15_REG \
    (CSR_MQM_DEQC_BASE + 0x33C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_16_REG \
    (CSR_MQM_DEQC_BASE + 0x340) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_17_REG \
    (CSR_MQM_DEQC_BASE + 0x344) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_18_REG \
    (CSR_MQM_DEQC_BASE + 0x348) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_19_REG \
    (CSR_MQM_DEQC_BASE + 0x34C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_20_REG \
    (CSR_MQM_DEQC_BASE + 0x350) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_21_REG \
    (CSR_MQM_DEQC_BASE + 0x354) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_22_REG \
    (CSR_MQM_DEQC_BASE + 0x358) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_23_REG \
    (CSR_MQM_DEQC_BASE + 0x35C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_24_REG \
    (CSR_MQM_DEQC_BASE + 0x360) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_25_REG \
    (CSR_MQM_DEQC_BASE + 0x364) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_26_REG \
    (CSR_MQM_DEQC_BASE + 0x368) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_27_REG \
    (CSR_MQM_DEQC_BASE + 0x36C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_28_REG \
    (CSR_MQM_DEQC_BASE + 0x370) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_29_REG \
    (CSR_MQM_DEQC_BASE + 0x374) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_30_REG \
    (CSR_MQM_DEQC_BASE + 0x378) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_31_REG \
    (CSR_MQM_DEQC_BASE + 0x37C) /* ENMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_0_REG \
    (CSR_MQM_DEQC_BASE + 0x380) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_1_REG \
    (CSR_MQM_DEQC_BASE + 0x384) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_2_REG \
    (CSR_MQM_DEQC_BASE + 0x388) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_3_REG \
    (CSR_MQM_DEQC_BASE + 0x38C) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_4_REG \
    (CSR_MQM_DEQC_BASE + 0x390) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_5_REG \
    (CSR_MQM_DEQC_BASE + 0x394) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_6_REG \
    (CSR_MQM_DEQC_BASE + 0x398) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_7_REG \
    (CSR_MQM_DEQC_BASE + 0x39C) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_8_REG \
    (CSR_MQM_DEQC_BASE + 0x3A0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_9_REG \
    (CSR_MQM_DEQC_BASE + 0x3A4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_10_REG \
    (CSR_MQM_DEQC_BASE + 0x3A8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_11_REG \
    (CSR_MQM_DEQC_BASE + 0x3AC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_12_REG \
    (CSR_MQM_DEQC_BASE + 0x3B0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_13_REG \
    (CSR_MQM_DEQC_BASE + 0x3B4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_14_REG \
    (CSR_MQM_DEQC_BASE + 0x3B8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_15_REG \
    (CSR_MQM_DEQC_BASE + 0x3BC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_16_REG \
    (CSR_MQM_DEQC_BASE + 0x3C0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_17_REG \
    (CSR_MQM_DEQC_BASE + 0x3C4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_18_REG \
    (CSR_MQM_DEQC_BASE + 0x3C8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_19_REG \
    (CSR_MQM_DEQC_BASE + 0x3CC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_20_REG \
    (CSR_MQM_DEQC_BASE + 0x3D0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_21_REG \
    (CSR_MQM_DEQC_BASE + 0x3D4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_22_REG \
    (CSR_MQM_DEQC_BASE + 0x3D8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_23_REG \
    (CSR_MQM_DEQC_BASE + 0x3DC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_24_REG \
    (CSR_MQM_DEQC_BASE + 0x3E0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_25_REG \
    (CSR_MQM_DEQC_BASE + 0x3E4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_26_REG \
    (CSR_MQM_DEQC_BASE + 0x3E8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_27_REG \
    (CSR_MQM_DEQC_BASE + 0x3EC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_28_REG \
    (CSR_MQM_DEQC_BASE + 0x3F0) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_29_REG \
    (CSR_MQM_DEQC_BASE + 0x3F4) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_30_REG \
    (CSR_MQM_DEQC_BASE + 0x3F8) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_31_REG \
    (CSR_MQM_DEQC_BASE + 0x3FC) /* ENFMQ Priority Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_0_REG \
    (CSR_MQM_DEQC_BASE + 0x400) /* ENMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_1_REG \
    (CSR_MQM_DEQC_BASE + 0x404) /* ENMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_2_REG \
    (CSR_MQM_DEQC_BASE + 0x408) /* ENMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_3_REG \
    (CSR_MQM_DEQC_BASE + 0x40C) /* ENMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_0_REG \
    (CSR_MQM_DEQC_BASE + 0x410) /* ENFMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_1_REG \
    (CSR_MQM_DEQC_BASE + 0x414) /* ENFMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_2_REG \
    (CSR_MQM_DEQC_BASE + 0x418) /* ENFMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_3_REG \
    (CSR_MQM_DEQC_BASE + 0x41C) /* ENFMQ Host Node Weight Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_0_REG \
    (CSR_MQM_DEQC_BASE + 0x420) /* ENMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_1_REG \
    (CSR_MQM_DEQC_BASE + 0x424) /* ENMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_2_REG \
    (CSR_MQM_DEQC_BASE + 0x428) /* ENMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_3_REG \
    (CSR_MQM_DEQC_BASE + 0x42C) /* ENMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_0_REG \
    (CSR_MQM_DEQC_BASE + 0x430) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_1_REG \
    (CSR_MQM_DEQC_BASE + 0x434) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_2_REG \
    (CSR_MQM_DEQC_BASE + 0x438) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_3_REG \
    (CSR_MQM_DEQC_BASE + 0x43C) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */
#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_0_REG \
    (CSR_MQM_DEQC_BASE + 0x440) /* DEQC SERVICE Node Shaper Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_1_REG \
    (CSR_MQM_DEQC_BASE + 0x444) /* DEQC SERVICE Node Shaper Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_ROOT_SHAP_CFG_REG \
    (CSR_MQM_DEQC_BASE + 0x450) /* DEQC ROOT Node Shaper Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_SHAP_BYPASS_CFG_REG (CSR_MQM_DEQC_BASE + 0x500) /* DEQC Shaper Bypass Configuration */
#define CSR_MQM_DEQC_DEQC_SPCOS_SHARE_RSC_XON_RSP_CFG_REG \
    (CSR_MQM_DEQC_BASE + 0x504) /* DEQC Spcos Share Resource XON Response Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_RH_XON_CFG_REG \
    (CSR_MQM_DEQC_BASE + 0x508) /* NFMQ ROOT SERVICE Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NMQ_REG \
    (CSR_MQM_DEQC_BASE + 0x50C) /* NMQ HOST Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NFMQ_REG \
    (CSR_MQM_DEQC_BASE + 0x510) /* NFMQ HOST Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NMQ_REG \
    (CSR_MQM_DEQC_BASE + 0x514) /* NMQ EP Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NFMQ_REG \
    (CSR_MQM_DEQC_BASE + 0x518) /* NFMQ EP Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_0_REG \
    (CSR_MQM_DEQC_BASE + 0x520) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_1_REG \
    (CSR_MQM_DEQC_BASE + 0x524) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_2_REG \
    (CSR_MQM_DEQC_BASE + 0x528) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_3_REG \
    (CSR_MQM_DEQC_BASE + 0x52C) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_4_REG \
    (CSR_MQM_DEQC_BASE + 0x530) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_5_REG \
    (CSR_MQM_DEQC_BASE + 0x534) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_6_REG \
    (CSR_MQM_DEQC_BASE + 0x538) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_7_REG \
    (CSR_MQM_DEQC_BASE + 0x53C) /* NMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_0_REG \
    (CSR_MQM_DEQC_BASE + 0x540) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_1_REG \
    (CSR_MQM_DEQC_BASE + 0x544) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_2_REG \
    (CSR_MQM_DEQC_BASE + 0x548) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_3_REG \
    (CSR_MQM_DEQC_BASE + 0x54C) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_4_REG \
    (CSR_MQM_DEQC_BASE + 0x550) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_5_REG \
    (CSR_MQM_DEQC_BASE + 0x554) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_6_REG \
    (CSR_MQM_DEQC_BASE + 0x558) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_7_REG \
    (CSR_MQM_DEQC_BASE + 0x55C) /* NFMQ COS Node Xon Configuration Table Register */
#define CSR_MQM_DEQC_DEQC_ROOT_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x560)         /* Root Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x564)  /* ENMQ Service Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NFMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x568) /* ENFMQ Service Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x56C)     /* ENMQ Host Node XON Table */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x570)    /* ENFMQ Host Node XON Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x574)  /* ENMQ host_ep Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x578) /* ENFMQ host_ep Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SPASS_ST_REG (CSR_MQM_DEQC_BASE + 0x57C) /* ENMQ Host Node Shaping Pass Flag Table \
                                                                             */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_PASS_ST_REG \
    (CSR_MQM_DEQC_BASE + 0x580)                                            /* ENFMQ Host Node Shaping Pass Flag Table */
#define CSR_MQM_DEQC_DEQC_FIFO_DFX_REG (CSR_MQM_DEQC_BASE + 0x584)         /* DEQC FIFO Empty and Full DFX Register. */
#define CSR_MQM_DEQC_DEQC_NMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C0)   /* ENMQ UP descpt count Register. */
#define CSR_MQM_DEQC_DEQC_NFMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C4)  /* ENFMQ UP descpt count Register. */
#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C8)  /* ENMQ Deq descpt count Register. */
#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5CC) /* ENFMQ Deq descpt count Register. */
#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D0)  /* ENMQ Deq cmd count Register. */
#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D4) /* ENFMQ Deq cmd count Register. */
#define CSR_MQM_DEQC_DEQC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D8) /* DEQC Non-filter MQ EMPT schedule count \
                                                                             */
#define CSR_MQM_DEQC_DEQC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5DC)  /* DEQC Normal MQ EMPT schedule count */
#define CSR_MQM_DEQC_DEQC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E0)  /* DEQC MEMORY ECC 1BIT ERR count */
#define CSR_MQM_DEQC_DEQC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E4)  /* DEQC MEMORY ECC 2BIT ERR count */
#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_CFG_REG (CSR_MQM_DEQC_BASE + 0x5E8)    /* DEQC_MQ DFX NUM configure */
#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_DEQC_BASE + 0x5EC) /* DEQC_MQ DFX NUM  ENQ UP count */
#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F0) /* DEQC_MQ DFX NUM  DEQ CMD count */
#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_NUM_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F4) /* DEQC_MQ DFX NUM  DEQ NUM count */
#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_EMPT_SCH_CNT_REG \
    (CSR_MQM_DEQC_BASE + 0x5F8) /* DEQC_MQ DFX NUM  DEQ EMPT SCH count */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_0_REG \
    (CSR_MQM_DEQC_BASE + 0x600) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_1_REG \
    (CSR_MQM_DEQC_BASE + 0x604) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_2_REG \
    (CSR_MQM_DEQC_BASE + 0x608) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_3_REG \
    (CSR_MQM_DEQC_BASE + 0x60C) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_4_REG \
    (CSR_MQM_DEQC_BASE + 0x610) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_5_REG \
    (CSR_MQM_DEQC_BASE + 0x614) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_6_REG \
    (CSR_MQM_DEQC_BASE + 0x618) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_7_REG \
    (CSR_MQM_DEQC_BASE + 0x61C) /* ENMQ host_ep_cos Node XON State Table */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_0_REG \
    (CSR_MQM_DEQC_BASE + 0x620) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_1_REG \
    (CSR_MQM_DEQC_BASE + 0x624) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_2_REG \
    (CSR_MQM_DEQC_BASE + 0x628) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_3_REG \
    (CSR_MQM_DEQC_BASE + 0x62C) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_4_REG \
    (CSR_MQM_DEQC_BASE + 0x630) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_5_REG \
    (CSR_MQM_DEQC_BASE + 0x634) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_6_REG \
    (CSR_MQM_DEQC_BASE + 0x638) /* ENFMQ host_ep_cos Node XON State Table0 */
#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_7_REG \
    (CSR_MQM_DEQC_BASE + 0x63C) /* ENFMQ host_ep_cos Node XON State Table0 */

#endif // MQM_REG_OFFSET_H
